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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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AFR
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ASCHENBRENNER, R A., FLYNN, M J ; AND ROBINSON, G. A "Intrinsic multiprocessing," Proc AF1PS, 1967 Spring Jr. Computer Conf, Vol 30, AFIPS Press, Montvale, N J, 1967, pp 81-86
|
| |
AGU
|
Auo, A V.; GAREY, M R , AND ULLMAN, J D "The transitive reduction of a directed graph," SIAM J Computers, l, 2 (June 1972), 131-137
|
| |
AST
|
ANDERSON, D W , SPARAClO, F j.; AN~) TOMASULO, R M "The IBM System/360 model 91: machine philosophy and instruction handhng " IBM J R&D, 11, 1 (Jan 1967), 8-24.
|
| |
B
|
BERNSTEIN, A J "Program analysis for parallel processing," IEEE TriEs Electronw Computers, EC-15, (Oct 1966), 757-762.
|
| |
Co
|
COFFMAN, E G "A formal microprogram model of parallelism and register sharing," Symposzum o1~ Computers at~d Automata, Polytechmc Institute of Brooklyn, New York, (April 1971), 215- 223.
|
| |
Cr
|
CRAY RESEARCH, INC CRAY-1 Prebml~ary Refere~ce Mal~ual (Draft), (Feb 197.5)
|
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Da
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D~VlS, E W "Concurrent processing of conditional jump trees," IEEE Compcot~ '72, IEEE, New York, (Sept 1972), 279-281
|
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De
|
DENNIS, J B "Modular, asynchronous control structures for a h~gh performance processor," A CM Co~f Record, Pro3ect MAC Col~f on Cow, current Systems and Parallel Computatzon, (June 1970), 55-80
|
| |
DM
|
DENNIS, J B , AND MISUNAS, D. P "A preliminary architecture for a basic dataflow processor," MIT Project MAC Computation Structures Group Memo 102 (August 1974)
|
| |
E
|
ELSPAS, B, ET AL "Investigation of propagation-limited computer networks," Stanford Research Institute Report AFCRL-64-376 (III). AD 637 769 (June 1966)
|
| |
FPS
|
FLYNN, M J.; PODVIN, A , AND SHIMIZU, K. "A multiple instruction stream processor with shared resources," in Parallel processor systems, technologies, and apphcat~o~s, Spartan Books, Wash- Ington, D C , 1970. pp 251-286
|
| |
G1
|
GRAHAM, R L. "Bounds on multiprocessing timing anomalies," SIAM J Appl. Math, 17, 2, (March 1969), 416-429
|
| |
G2
|
GRAHAM, R L "Bounds on multiprocessing anomalies and related packing algorithms," Proc AFIPS 1972 Sprang Jt Computer Conf, Vol 40, AFIPS Press Montvale, N J., 1972, pp 205-217
|
| |
H
|
HARPER, S. D. "Automatic parallel processing," Proc Computing a~d Data Process, t~g Society of Canada, Second Conference, (June 1960), 321-331
|
| |
HT
|
HENTZ, R G , AND TATE, G P "Control Data Star-100 processor design," IFEE Proc Compcolt '72, IEEE, New York, (Sept 1972), 1-4.
|
| |
KM1
|
KARP, R M ; AND MILLER, R E "Propertms of a model for parallel computations: determinacy, termination, queuerag," SIAM J A ppl. Math, 14, 6 (Nov 1966), 1390-1411.
|
| |
KM2
|
KARP, R. M., AND MII,LER, R. E. "Parallel program schemata," J Cornpurer & System Sc~eTtces 3, 2 (May 1969), 147-195
|
 |
Ke
|
|
| |
KMC
|
KUCK, l) J , MURAOKA, Y ; AND CHEN, S-C "On the number of operatmns simultaneously executable m FORTRAN- like programs and their resulting speedup," IEEE Tratts Computers, C-21, 12 (Dec 1972), 1293-1309
|
| |
MC
|
|
 |
MT
|
|
| |
Ro
|
ROHRBACHER, D L Adva~ced computer orgat~,zaho~ study, Rome Air Development Corp, Tech Report RADC-TR-66- 7 (2 vols ) AD 631 870, and 631 871 (April 1966)
|
| |
S
|
STONE, H S. "A pipeline push-down stack computer," in Parallel processor systems, technologies, at~d application, s, Spartan Books, Washington, D C , 1970, pp. 235-249
|
| |
Th
|
|
| |
To
|
TOMASULO, R M "An efficient algorithm for exploiting multiple arithmetic units," IBM J R&D, II, 1 (Jan 1967), 25-33
|
 |
U
|
|
 |
War
|
|
| |
Wat
|
WATSON,W J "The Texas Instruments Advanced Scientific Computer," 1EEE Proc Compcon '72, IEEE, New York, (Sept. 1972), 291-293.
|
 |
1
|
|
 |
2
|
|
| |
3
|
CHEN, T C. "The overlap design of the IFM System/360 model 92 central processing unit," Proc. AF1PS 1964 Sprang Jt Computer Conf., Vol 25 AFIPS Press, Montvale, N J., 1964, pp 73-80
|
| |
4
|
FLYNN, M J "Some computer orgamzations and their effectiveness," 1EEE Trans. Computers, C-21, 9 (Sept. 1972), 948-960.
|
| |
5
|
FOSTER, C. C ;AND PtISEMAN, E. M "Percolation of code to enhance parallel dmpatching and execution," IEEE Trans Computers, C-21, 12 (Dec. 1972), 1411-1415
|
| |
6
|
FRANKOVICH, J. M.; AND PETERSON, H. P. "A functional description of the Lincoln TX-2 computer," Proc. Western Jr. Computer Conf." (Feb. 1957), 146-155.
|
| |
7
|
GnAHAM, W.R. "The parallel and the pipeline computers," Datamatzon, 16, 4 (April 1970), 68-71.
|
| |
8
|
IBBETT, R N. "TheMU5 instruction p,peline," Computer J., 15, 1 (Feb 1972), 42-47.
|
| |
9
|
LoGRIPPO, L. "Renaming in program sche. mas," Proc. IEEE 18th-Annual Symposzum on Switchzng and Automata Theory, (Oct 1972), 67-7O
|
| |
10
|
MILLER, E.F. "A multiple-stream register less sh~red-resource processor," IEFE Trans. Computers C,23, 3 (March 1974~ 277-285.~
|
| |
11
|
REIGEL, E. W. Parallehsm exposure o~d exploitation ~n d~g~al computing system.~. Tech. Report TR-69-4, Burroughs Corp., Defense, Space, and Special Systems Group, 1969
|
| |
12
|
RISEMAN, E. M ; AND FOSTER, C C "The inhibition of parallelism by conditional jumps," 1EEE Trans. Computers, C-21, 12 (Dec 1972), 1405-1410.
|
| |
13
|
SHEMEa, J E., ~NV GUPTA, S.C. "A simphfied ana{ysis of processor look-ahead and simultaneous operation of a multiple-module mare memory," 1EEE Trans. Computers, C.18, 1 (Jan. 1969), 64-71.
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CITED BY 47
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Augustus K. Uht , Constantine D. Polychronopoulos , John F. Kolen, On the combination of hardware and software concurrency extraction methods, Proceedings of the 20th annual workshop on Microprogramming, p.133-141, December 01-04, 1987, Colorado Springs, Colorado, United States
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Mayan Moudgill , Keshav Pingali , Stamatis Vassiliadis, Register renaming and dynamic speculation: an alternative approach, Proceedings of the 26th annual international symposium on Microarchitecture, p.202-213, December 01-03, 1993, Austin, Texas, United States
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Ashok Sudarsanam , Stan Liao , Srinivas Devadas, Analysis and evaluation of address arithmetic capabilities in custom DSP architectures, Proceedings of the 34th annual conference on Design automation, p.287-292, June 09-13, 1997, Anaheim, California, United States
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Stephen Jourdan , Ronny Ronen , Michael Bekerman , Bishara Shomar , Adi Yoaz, A novel renaming scheme to exploit value temporal locality through physical register reuse and unification, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.216-225, November 1998, Dallas, Texas, United States
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Matthew K. Farrens , Pius Ng , Phil Nico, A comparision of superscalar and decoupled access/execute architectures, Proceedings of the 26th annual international symposium on Microarchitecture, p.100-103, December 01-03, 1993, Austin, Texas, United States
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Val Popescu , Merle Schultz , John Spracklen , Gary Gibson , Bruce Lightner , David Isaman, The Metaflow Architecture, IEEE Micro, v.11 n.3, p.10-13, 63-73, May 1991
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Sung-Soo Lim , Young Hyun Bae , Gyu Tae Jang , Byung-Do Rhee , Sang Lyul Min , Chang Yun Park , Heonshik Shin , Kunsoo Park , Soo-Mook Moon , Chong Sang Kim, An Accurate Worst Case Timing Analysis for RISC Processors, IEEE Transactions on Software Engineering, v.21 n.7, p.593-604, July 1995
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