Adapting software pipelining for reconfigurable computing

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Adapting software pipelining for reconfigurable computing

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International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems table of contents

San Jose, California, United States

Pages: 57 - 64

Year of Publication: 2000

ISBN:1-58113-338-3

Authors

Timothy J. Callahan	University of California at Berkeley
John Wawrzynek	University of California at Berkeley

Sponsor

ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 48, Citation Count: 16

Additional Information:

cited by collaborative colleagues

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CITED BY 16

	Greg Snider, Performance-constrained pipelining of software loops onto reconfigurable hardware, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Alberto La Rosa , Luciano Lavagno , Claudio Passerone, A software development tool chain for a reconfigurable processor, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
	Heidi E. Ziegler , Mary W. Hall , Pedro C. Diniz, Compiler-generated communication for pipelined FPGA applications, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Reiner Hartenstein, The digital divide of computing, Proceedings of the 1st conference on Computing frontiers, April 14-16, 2004, Ischia, Italy
	Andrea Lodi , Mario Toma , Fabio Campi, A pipelined configurable gate array for embedded processors, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Binu Mathew , Al Davis , Mike Parker, A low power architecture for embedded perception, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
	Heidi Ziegler , Mary Hall, Evaluating heuristics in automatically mapping multi-loop applications to FPGAs, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Joäo M. P. Cardoso, Dynamic loop pipelining in data-driven architectures, Proceedings of the 2nd conference on Computing frontiers, May 04-06, 2005, Ischia, Italy
	Partha Biswas , Nikil Dutt , Paolo Ienne , Laura Pozzi, Automatic identification of application-specific functional units with architecturally visible storage, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Mahim Mishra , Timothy J. Callahan , Tiberiu Chelcea , Girish Venkataramani , Seth C. Goldstein , Mihai Budiu, Tartan: evaluating spatial computation for whole program execution, ACM SIGOPS Operating Systems Review, v.40 n.5, December 2006
	Tarvo Raudvere , Ingo Sander , Axel Jantsch, A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Bingfeng Mei , Serge Vernalde , Diederik Verkest , Hugo De Man , Rudy Lauwereins, Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling, Proceedings of the conference on Design, Automation and Test in Europe, p.10296, March 03-07, 2003
	Alberto La Rosa , Luciano Lavagno , Claudio Passerone, Hardware/Software Design Space Exploration for a Reconfigurable Processor, Proceedings of the conference on Design, Automation and Test in Europe, p.10570, March 03-07, 2003
	Alberto La Rosa , Claudio Passerone , Francesco Gregoretti , Luciano Lavagno, Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform, Proceedings of the conference on Design, automation and test in Europe, p.21218, February 16-20, 2004
	Tameesh Suri, Improving instruction level parallelism through reconfigurable units in superscalar processors, ACM SIGARCH Computer Architecture News, v.35 n.3, June 2007
	Grigorios Dimitroulakos , Stavros Georgiopoulos , Michalis D. Galanis , Costas E. Goutis, Resource aware mapping on coarse grained reconfigurable arrays, Microprocessors & Microsystems, v.33 n.2, p.91-105, March, 2009

Collaborative Colleagues:

Timothy J. Callahan: colleagues

John Wawrzynek: colleagues

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