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A preprocessing step for global loop transformations for data transfer optimization
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Source International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems table of contents
San Jose, California, United States
Pages: 34 - 40  
Year of Publication: 2000
ISBN:1-58113-338-3
Authors
Koen Danckaert  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Francky Catthoor  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Hugo De Man  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 12,   Downloads (12 Months): 31,   Citation Count: 8
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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[2] S. Amarasinghe, J. Anderson, M. Lam, and C. Tseng, "The SUIF compiler for scalable parallel machines", Proc. of the 7th SIAM Conf. on Parallel Proc. for Scientific Computing, 1995.
 
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[4] U. Banerjee, R. Eigenmann, A. Nicolau, D. Padua, "Automatic program parallelisation", Proc. of the IEEE, invited paper, Vol. 81, No. 2, Feb. 1993.
 
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[5] E. Brockmeyer, L. Nachtergaele, F. Catthoor, J. Bormans, H. De Man, "Low power memory storage and transfer organization for the MPEG-4 full pel motion estimation on a multi media processor", IEEE Trans. on Multi-Media, Vol. 1, No. 2, pp. 202-216, June 1999.
 
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[6] F. Catthoor, S. Wuytack, E. De Greef, F. Franssen, L. Nachtergaele. H. De Man, "System-level transformations for low power data transfer and storage", in paper collection on "Low power CMOS design" (eds. A. Chandrakasan, R. Brodersen), IEEE Press, pp. 609-618, 1998.
 
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[10] E. De Greef, F. Catthoor, H. De Man, "Memory Size Reduction through Storage Order Optimization for Embedded Parallel Multimedia Applications", Intnl. Parallel Proc. Symp. (IPPS) in Proc. Workshop on "Parallel Processing and Multimedia", Geneva, Switzerland, pp. 84-98, 1997.
 
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[11] H. De Man, F. Catthoor, G. Goossens, J. Vanhoof, J. Van Meerbergen, S. Note, J. Huisken, "Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms", Proc. of the IEEE, special issue on "The future of computer-aided Design", Vol. 78, No. 2, pp. 319-335, Feb. 1990.
 
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[14] P. Feautrier, "Automatic parallelization in the polytope model", to appear.
 
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[25] M. van Swaaij, F. Franssen, F. Catthoor, H. De Man, "Automating high-level control flow transformations for DSP memory management", Proc. IEEE workshop on VLSI signal processing, Napa Valley CA, Oct. 1992.
 
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CITED BY  8
Collaborative Colleagues:
Koen Danckaert: colleagues
Francky Catthoor: colleagues
Hugo De Man: colleagues