| Optimizing software performance for IP frame reassembly in an integrated architecture |
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Workshop on Software and Performance
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Proceedings of the 2nd international workshop on Software and performance
table of contents
Ottawa, Ontario, Canada
Pages: 29 - 37
Year of Publication: 2000
ISBN:1-58113-195-X
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Authors
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Peter M. Ewert
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Dept. of Electrical and Computer Engineering, Queen's University, Kingston, Ontario, Canada K7L 3N6
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Naraig Manjikian
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Dept. of Electrical and Computer Engineering, Queen's University, Kingston, Ontario, Canada K7L 3N6
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Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 0
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Elkateeb, A., and M. Elbeshti. "An evaluation of the AAL and ATM protocols processing requirements for the network interfaces design." In Proceedings of the 1999 Symposium on Performance Evaluation of Computer and Telecommunication Systems, Chicago, IL., July 1999, pp. 13-16.
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R. F. Hobson and K. L. Cheung, "A High-Performance CMOS 32-Bit Parallel CRC Engine." IEEE Journal of Solid-State Circuits, Vol. 34, No.2, February 1999, pp. 233- 235.
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IBM Corporation, "Synchronous DRAMS: The DRAM of the Future," IBM MicroNews, First Quarter 1996. http://www.chips.ibm.com.
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N. Manjikian and P. R. McHardy. "An object-oriented framework for execution-driven architectural simulation." In Proceedings of the 1999 Symposium on Performance Evaluation of Computer and Telecommunication Systems, Chicago, IL., July 1999, pp. 227-231.
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Motorola Corporation, "MPC7400 RISC Microprocessor Technical Summary," Document MPC7400TS/D, Rev. 0, August 1999. http://www.motorola.com/SPS/PowerPC/AltiVec
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David Patterson , Thomas Anderson , Neal Cardwell , Richard Fromm , Kimberly Keeton , Christoforos Kozyrakis , Randi Thomas , Katherine Yelick, A Case for Intelligent RAM, IEEE Micro, v.17 n.2, p.34-44, March 1997
[doi> 10.1109/40.592312]
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