ACM Home Page
Please provide us with feedback. Feedback
Digital Library logoTake a look at the new version of this page: [ beta version ]. Tell us what you think.
Optimal instruction scheduling using integer programming
Full text PdfPdf (831 KB)
Source Conference on Programming Language Design and Implementation archive
Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation table of contents
Vancouver, British Columbia, Canada
Pages: 121 - 133  
Year of Publication: 2000
ISBN:1-58113-199-2
Also published in ...
Authors
Kent Wilken  Department of Electrical and Computer Engineering, University of California, Davis, CA
Jack Liu  Department of Electrical and Computer Engineering, University of California, Davis, CA
Mark Heffernan  Department of Electrical and Computer Engineering, University of California, Davis, CA
Sponsors
SIGPLAN: ACM Special Interest Group on Programming Languages
SIGSOFT: ACM Special Interest Group on Software Engineering
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 103,   Citation Count: 14
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/349299.349318
What is a DOI?

ABSTRACT

This paper presents a new approach to local instruction scheduling based on integer programming that produces optimal instruction schedules in a reasonable time, even for very large basic blocks. The new approach first uses a set of graph transformations to simplify the data-dependency graph while preserving the optimality of the final schedule. The simplified graph results in a simplified integer program which can be solved much faster. A new integer-programming formulation is then applied to the simplified graph. Various techniques are used to simplify the formulation, resulting in fewer integer-program variables, fewer integer-program constraints and fewer terms in some of the remaining constraints, thus reducing integer-program solution time. The new formulation also uses certain adaptively added constraints (cuts) to reduce solution time. The proposed optimal instruction scheduler is built within the Gnu Compiler Collection (GCC) and is evaluated experimentally using the SPEC95 floating point benchmarks. Although optimal scheduling for the target processor is considered intractable, all of the benchmarks' basic blocks are optimally scheduled, including blocks with up to 1000 instructions, while total compile time increases by only 14%.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
S. Arya. An Optimal Instruction-Scheduling Model for a Class of Vector Processors. IEEE Transactions on Computers, C-34(11):981-995, November 1985.
2
 
3
 
4
 
5
C-M Chang, C-M Chen, and C-T King. Using Integer Linear Programming for Instruction Scheduling and Register Allocation in Multi-Issue Processors. Computers and Mathematics with Applications, 34(9):1-14, November 1997.
 
6
 
7
 
8
A. Ertl and A. Krall. Optimal Instruction Scheduling Using Constraint Logic Programming. In Programming Language Implementation and Logic Programming (PLILP). Springer-Verlag, 1991.
 
9
 
10
J. Grossman. Discrete Mathematics. Macmillan, 1990.
 
11
 
12
ILOG. ILOG CPLEX 6.5 User's Manual. ILOG, 1999.
 
13
C. Kessler. Scheduling Expression DAGs for Miniml Register Need. Computer Languages, 24(1):33-53, April 1998.
 
14
 
15
 
16
G. Nemhauser. The Age of Optimization: Solving Large-Scale Real-World Problems. Operations Research, 42(1):5-13, Jan.-Feb. 1994.
17
18
19
 
20
M. Savelsbergh. Preprocessing and Probing for Mixed Integer Programming Problems. ORSA Journal of Computing, 6(4):445-454, Fall 1994.
 
21
P. Sweany and S. Beaty. Instruction Scheduling Using Simulated Annealing. In Proc. 3rd International Conference on Massively Parallel Computing Systems (MPCS '98), 1998.
 
22
H. Tomiyama, T. Ishihara, A. Inoue, and H. Yasuura. Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches. IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E81-A(12):2621- 2629, December 1998.
 
23
 
24
Laurence A. Wolesey. Integer Programming. John Wiley &; Sons, Inc., 1998.

CITED BY  14

Collaborative Colleagues:
Kent Wilken: colleagues
Jack Liu: colleagues
Mark Heffernan: colleagues