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Optimizing computations for effective block-processing
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Source ACM Transactions on Design Automation of Electronic Systems (TODAES) archive
Volume 5 ,  Issue 3  (July 2000) table of contents
Pages: 604 - 630  
Year of Publication: 2000
ISSN:1084-4309
Authors
Kumar N. Lalgudi  Intel Corp., Hillsboro, OR
Marios C. Papaefthymiou  Univ. of Michigan, Ann Arbor
Miodrag Potkonjak  Univ. of California, Los Angeles
Publisher
ACM  New York, NY, USA
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ABSTRACT

Block-processing can decrease the time and power required to perform any given computation by simultaneously processing multiple samples of input data. The effectiveness of block-processing can be severely limited, however, if the delays in the dataflow graph of the computation are placed suboptimally. In this paper we investigate the application of retiming for improving the effectiveness of block-processing in computations. In particular, we consider the k-delay problem: Given a computation dataflow graph and a positive integer k, we wish to compute a retimed computation graph in which the original delays have been relocated so that k data samples can be processed simultaneously and fully regularly. We give an exact integer linear programming formulation for the k-delay problem. We also describe an algorithm that solves the k-delay problem fast in practice by relying on a set of necessary conditions to prune the search space. Experimental results with synthetic and random benchmarks demonstrate the performance improvements achievable by block-processing and the efficiency of our algorithm.


REFERENCES

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1
 
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CHERKASSKY, B., GOLDBERG, A., AND RADZIK, T. 1993. Shortest paths algorithms:: theory and experimental evaluation. Tech. Rep. STAN-CS-93-1480. Stanford University, Stanford, CA.
 
3
 
4
DE MICHELI, G. 1991. Synchronous logic synthesis: Algorithms for cycle-time optimization. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 10, 1 (Jan. 1991), 63-73.
 
5
GIBBS, W. W. 1994. Software's chronic crisis. Sci. Am. (Sept. 1994), 86-95.
 
6
GUERRA, L., POTKONJAK, M., AND RABAEY, J. 1994. System-level design guidance using algorithm properties. In Proceedings of the IEEE Workshop on VLSI Signal Processing VII, IEEE Press, Piscataway, NJ, 73-82.
 
7
ISHII, A. T., LEISERSON, C. E., AND PAPAEFTHYMIOU, M. C. 1992. Optimizing two-phase, level-clocked circuitry. In Proceedings of the 1992 Brown/MIT Conference on Advanced Research in VLSI and Parallel Systems, T. Knight and J. Savage, Eds. MIT Press, Cambridge, MA, 245-264.
 
8
Ku, D. C. AND DE MICHELI, G. 1992. Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits. IEEE Trans. CAD/ICAS 11, 6 (June), 696-718.
 
9
10
 
11
 
12
LEISERSON, C. E. AND SAXE, J. B. 1991. Retiming synchronous circuitry. Algorithmica 6, 1, 5-35.
13
 
14
 
15
MALIK, S., SENTOVICH, E., BRAYTON, R. K., AND SANGIOVANNI-VINCENTELLI, A. 1990. Retiming and resynthesis: Optimizing sequential networks with combinational techniques. In Proceedings of the 23rd Annual Hawaii International Conference on System Sciences, 397-406.
 
16
RITZ, S., PANKERT, M., ZIVOJNOVIC, V., AND MEYR, H. 1993. Optimum vectorization of scalable synchronous dataflow graphs. In Proceedings of the International Conference on Application-Specific Array Processors (Oct. 1993), 285-296.
 
17
WALKER, R. A. AND THOMAS, D. E. 1989. Behavioral transformations for algorithmic level IC design. IEEE Trans. CAD/ICAS 8, 10 (Oct.), 1115-1127.
 
18
ZIVOJNOVIC, V., RITZ, S., AND MEYR, H. 1994. Retiming of DSP programs for optimum vectorization. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing 2, 19-22.


Collaborative Colleagues:
Kumar N. Lalgudi: colleagues
Marios C. Papaefthymiou: colleagues
Miodrag Potkonjak: colleagues