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Synthesis of low-power selectively-clocked systems from high-level specification
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Source ACM Transactions on Design Automation of Electronic Systems (TODAES) archive
Volume 5 ,  Issue 3  (July 2000) table of contents
Pages: 311 - 321  
Year of Publication: 2000
ISSN:1084-4309
Authors
L. Benini  Univ. di Bologna, Bologna, Italy
G. De Micheli  Stanford Univ., Stanford, CT
Publisher
ACM  New York, NY, USA
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ABSTRACT

We propose a technique for synthesizing low-power systems from behavioral specifications. We analyze the control flow of the specification model to detect mutually exclusive sections of the computation. A selectively-clocked interconnection of interacting FSMs is automatically generated and optimized, where each FSM controls the execution of one section of computation. Only one of the interacting FSMs is active for a high fraction of the operation time, while the others are idle and their clocks are stopped. Periodically, the active machine releases the control of the system to another FSM and stops. Our interacting FSM implementation achieves consistently lower power dissipation than the functionally equivalent monolithic implementation. On average, 37% power savings and 12% speedup are obtained, despite a 30% area overhead.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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BENINI, L. AND DE MICHELI, G. 1996. Transformation and synthesis of FSMs for low power gated clock implementation. IEEE Trans. Comput.-Aided Des. Integr. Circuits 15, 6 (June 1996), 630-643.
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RABAEY, J. AND PEDRAM, M. 1996. Low Power Design Methodologies. Kluwer Academic, Dordrecht, Netherlands.

Collaborative Colleagues:
L. Benini: colleagues
G. De Micheli: colleagues