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Polygon rendering on a stream architecture
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Source SIGGRAPH/EUROGRAPHICS Conference On Graphics Hardware archive
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware table of contents
Interlaken, Switzerland
Pages: 23 - 32  
Year of Publication: 2000
ISBN:1-58113-257-3
Authors
John D. Owens  Computer Systems Laboratory, Stanford University, Gates Computer Science Building, 4A, Stanford, CA
William J. Dally  Computer Systems Laboratory, Stanford University, Gates Computer Science Building, 4A, Stanford, CA
Ujval J. Kapasi  Computer Systems Laboratory, Stanford University, Gates Computer Science Building, 4A, Stanford, CA
Scott Rixner  Computer Systems Laboratory, Stanford University, Gates Computer Science Building, 4A, Stanford, CA
Peter Mattson  Computer Systems Laboratory, Stanford University, Gates Computer Science Building, 4A, Stanford, CA
Ben Mowery  Computer Systems Laboratory, Stanford University, Gates Computer Science Building, 4A, Stanford, CA
Sponsors
Eurographics :
SIGGRAPH: ACM Special Interest Group on Computer Graphics and Interactive Techniques
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 9,   Downloads (12 Months): 72,   Citation Count: 14
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ABSTRACT

The use of a programmable stream architecture in polygon rendering provides a powerful mechanism to address the high performance needs of today's complex scenes as well as the need for flexibility and programmability in the polygon rendering pipeline. We describe how a polygon rendering pipeline maps into data streams and kernels that operate on streams, and how this mapping is used to implement the polgyon rendering pipeline on Imagine, a programmable stream processor. We compare our results on a cycle-accurate simulation of Imagine to representative hardware and software renderers.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Scott Rixner, William J. Dally, Brucek Khailany, Peter Mattson, Ujval Kapasi, and John D. Owens. Register organization for media processing. In Proceedings of the Sixth Annual International Symposium on High-Performance Computer Architecture, pages 375-386, 2000.
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CITED BY  14

Collaborative Colleagues:
John D. Owens: colleagues
William J. Dally: colleagues
Ujval J. Kapasi: colleagues
Scott Rixner: colleagues
Peter Mattson: colleagues
Ben Mowery: colleagues