| Profile-driven code execution for low power dissipation (poster session) |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2000 international symposium on Low power electronics and design
table of contents
Rapallo, Italy
Pages: 253 - 255
Year of Publication: 2000
ISBN:1-58113-190-9
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Author
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Diana Marculescu
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Dept. of Electrical and Computer Eng., Carnegie Mellon Univ., Pittsburgh, PA
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Downloads (6 Weeks): 1, Downloads (12 Months): 8, Citation Count: 10
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ABSTRACT
This paper proposes a novel technique for power-performance trade-off based on profile-driven code execution. Specifically, we show that there is an optimal level of parallelism for energy consumption and propose a compiler-assisted technique for code annotation that can be used at run-time to adaptively trade-off power and performance. As shown by experimental results, our approach is up to 23% better than clock throttling and is as efficient as voltage scaling (up to 10% better in some cases). The technique proposed in this paper can be used by an ACPI-compliant power manager for prolonging battery life or as a passive cooling feature for thermal management.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez, Reducing power in high-performance microprocessors, Proceedings of the 35th annual conference on Design automation, p.732-737, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277227]
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Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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Haris Lekatsas , Jörg Henkel , Wayne Wolf, Code compression for low power embedded system design, Proceedings of the 37th conference on Design automation, p.294-299, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337423]
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Hector Sanchez , Belli Kuttanna , Tim Olson , Mike Alexander , Gian Gerosa , Ross Philip , Jose Alvarez, Thermal Management System for High Performance PowerPCTM Microprocessors, Proceedings of the 42nd IEEE International Computer Conference, p.325, February 23-26, 1997
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G. Cai and C.H. Lira, 'Architectural Level Power/Performance Optimization and Dynamic Power Estimation,' in P~vc. MICRO-32 (Cool Chips tutorial), Nov. 1999.
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Advanced Configuration and Power Interface Specification,' Intel, Microsoft, Toshiba, Revision 1.0b, Feb. 2, 1999, at http://www.teleport.com/Nacpi/DOWN- LOAD S/A CPI~pec l Ob.pdf .
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D. Marculescu and S.W. Haga, 'Adaptive Execution Rate for Low Power in Superscalar Processors,' Technical Report 99-10, Dept. of ECE, UMD, Oct. 1999.
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D. Burger, T.M. Austin, 'The SimpleScalar Tool Set, Version 2.0,' CSD Technical Report #1342, University of Wisconsin-Madison, June 1997.
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D. Marculescu, 'ILP Exploration for Energy Optimization in Modem Processors,' Technical Report CMU-CEDA, Feb.2000.
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G. Cai, Personal communication, Feb. 2000.
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CITED BY 10
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Ismail Kadayif , Mahmut Kandemir , Guilin Chen , Ozcan Ozturk , Mustafa Karakoy , Ugur Sezer, Optimizing Array-Intensive Applications for On-Chip Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v.16 n.5, p.396-411, May 2005
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