A low power unified cache architecture providing power and performance flexibility (poster session)

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A low power unified cache architecture providing power and performance flexibility (poster session)

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents

Rapallo, Italy

Pages: 241 - 243

Year of Publication: 2000

ISBN:1-58113-190-9

Authors

Afzal Malik	M-CORE Technology Center, Motorola, Inc., P.O. Box 6000, MD TX77-F51, Austin, TX
Bill Moyer	M-CORE Technology Center, Motorola, Inc., P.O. Box 6000, MD TX77-F51, Austin, TX
Dan Cermak	M-CORE Technology Center, Motorola, Inc., P.O. Box 6000, MD TX77-F51, Austin, TX

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 73, Citation Count: 51

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

Advances in technology have allowed portable electronic devices to become smaller and more complex, placing stringent power and performance requirements on the devices components. The M7CORE M3 architecture was developed specifically for these embedded applications. To address the growing need for longer battery life and higher performance, an 8-Kbyte, 4-way set-associative, unified (instruction and data) cache with pro-grammable features was added to the M3 core. These features allow the architecture to be optimized based on the applications requirements. In this paper, we focus on the features of the M340 cache sub-system and illustrate the effect on power and perfor-mance through benchmark analysis and actual silicon measure-ments.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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