Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session)

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Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session)

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents

Rapallo, Italy

Pages: 231 - 233

Year of Publication: 2000

ISBN:1-58113-190-9

Author

Kanad Ghose

Dept. of Computer Science, State University of New York, Binghamton, NY

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 15, Citation Count: 6

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ABSTRACT

Recent studies [MGK 98, Tiw 98] have confirmed that a significant amount of energy is dissipated in the process of instruction dispatching and issue in modern superscalar microprocessors. We propose a model for the energy dissipated by instruction dispatching and issuing logic in modern superscalar microprocessors and validate them through register level simulations and SPICE-measured dissipation coefficients from 0.5 micron CMOS layouts of relevant circuits. Alternative organizations are studied for instruction window buffers that result in energy savings of about 47% over traditional designs.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	GhKa 99	Kanad Ghose , Milind B. Kamble, Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation, Proceedings of the 1999 international symposium on Low power electronics and design, p.70-75, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313860]
	MGK 98	Srilatha Manne , Artur Klauser , Dirk Grunwald, Pipeline gating: speculation control for energy reduction, Proceedings of the 25th annual international symposium on Computer architecture, p.132-141, June 27-July 02, 1998, Barcelona, Spain
	PJS 96	Palacharla, S., J ouppi, N. E and Smith, J.E., "Quantifying the complexity of superscalar processors", Technical report CS- TR-96-1308, Dept. of CS, Univ. of Wisconsin, 1996.
	Tiw 98	Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez, Reducing power in high-performance microprocessors, Proceedings of the 35th annual conference on Design automation, p.732-737, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277227]
	Vas 96	Vasseghi, N. et al, "200 MHz. Superscalar RISC processor circuit design issues", Proc. ISSCC digest of technical papers, 1996, pp. 356-357.

CITED BY 6

	Gurhan Kucuk , Kanad Ghose , Dimitry V. Ponomarev , Peter M. Kogge, Energy: efficient instruction dispatch buffer design for superscalar processors, Proceedings of the 2001 international symposium on Low power electronics and design, p.237-242, August 2001, Huntington Beach, California, United States
	Dmitry V. Ponomarev , Gurhan Kucuk , Oguz Ergin , Kanad Ghose , Peter M. Kogge, Energy-efficient issue queue design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.789-800, October 2003
	Michael Huang , Jose Renau , Josep Torrellas, Energy-efficient hybrid wakeup logic, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Steven Dropsho , Volkan Kursun , David H. Albonesi , Sandhya Dwarkadas , Eby G. Friedman, Managing static leakage energy in microprocessor functional units, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Francisco J. Mesa-Martínez , Michael C. Huang , Jose Renau, SEED: scalable, efficient enforcement of dependences, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
	Ali Mahjur , Mahmud Taghizadeh , Amir Hossein Jahangir, Lazy instruction scheduling: keeping performance, reducing power, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India