Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session)

ABSTRACT

Gate capacitance has complex voltage dependency on terminal voltages but the impact of this voltage dependency of gate capacitance on power and delay has not been fully investigated, especially, in low-voltage, low-power designs. Introducing an effective gate capacitance, CG, effit is shown that the power and delay of CMOS digital circuit can be estimated accurately. CG, effis a strong function of VTH/VDDand VTH/VDDtends to increase in low-voltage region. Hence, the effective capacitance (relative to oxide capacitance, CG, eff, is decreasing in low-voltage low-power designs. Therefore, considering CG, effin accurate power and delay) estimation becomes more important in the future.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Physics

General Terms:
Experimentation, Measurement, Performance

Keywords:
gate capacitance, low supply voltage, low-power design