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"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology (poster session)
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents
Rapallo, Italy
Pages: 203 - 206  
Year of Publication: 2000
ISBN:1-58113-190-9
Authors
R. V. Joshi  IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY
W. Hwang  IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY
S. C. Wilson  IBM System, 390 Division, Poughkeepsie, NY
C. T. Chuang  IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 7,   Downloads (12 Months): 25,   Citation Count: 1
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ABSTRACT

This paper describes power analysis at sub-zero temperatures for a high performance dynamic multiport register file (6 Read and 2 Write ports, 32 wordlines x 64 bitlines) fabricated in 0.25 &mgr;m Silicon on Insulator (SOI) and bulk technologies. Based on the hardware it is shown that the performance of both register file and latch improves by 2-3.5% per 10§ C reduction in temperature. The standby power for SOI reduces by 1.5% to 3 per 10§ C temperature drop down to -30§ C. The SOI chip is shown to have more significant performance improvement at low temperatures compared to bulk chip due to the floating body effect which partially offsets the increase in the threshold voltages (Vt). The low temperature performance gain is attributed to reduction in capacitance (around 7-8%) and rest is due to dynamic threshold voltages. At 30§ C the register file is capable of functioning close to 1.02 GHz for read and write operations in a single cycle.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
D.J. Schepis et al., "A 0.25"m CMOS SOI technology and its application to 4 Mb SRAM," Proc. IEDM, Dec 1997, pp.587-590.
 
2
R. V. Joshi et al., "A 666 MHz self-resetting 8 Port, 32x64 bits register "le and latch in 0.25"m SOI technology," Proc. 1998 IEEE Int. SOI Conf., Oct 1998, pp.131-132.
 
3
W. H. Henkels, W. Hwang and R. V. Joshi, "A 500 MHz 32-Word x 64-Bit 8-Port Self-Resetting CMOS Register le and associated dynamic-to-static latch," VLSI Design Symp., June 1997, pp.41-42.
4


Collaborative Colleagues:
R. V. Joshi: colleagues
W. Hwang: colleagues
S. C. Wilson: colleagues
C. T. Chuang: colleagues