| "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology (poster session) |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2000 international symposium on Low power electronics and design
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Rapallo, Italy
Pages: 203 - 206
Year of Publication: 2000
ISBN:1-58113-190-9
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Authors
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R. V. Joshi
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IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY
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W. Hwang
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IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY
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S. C. Wilson
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IBM System, 390 Division, Poughkeepsie, NY
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C. T. Chuang
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IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY
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Downloads (6 Weeks): 7, Downloads (12 Months): 25, Citation Count: 1
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ABSTRACT
This paper describes power analysis at sub-zero temperatures for a high performance dynamic multiport register file (6 Read and 2 Write ports, 32 wordlines x 64 bitlines) fabricated in 0.25 &mgr;m Silicon on Insulator (SOI) and bulk technologies. Based on the hardware it is shown that the performance of both register file and latch improves by 2-3.5% per 10§ C reduction in temperature. The standby power for SOI reduces by 1.5% to 3 per 10§ C temperature drop down to -30§ C. The SOI chip is shown to have more significant performance improvement at low temperatures compared to bulk chip due to the floating body effect which partially offsets the increase in the threshold voltages (Vt). The low temperature performance gain is attributed to reduction in capacitance (around 7-8%) and rest is due to dynamic threshold voltages. At 30§ C the register file is capable of functioning close to 1.02 GHz for read and write operations in a single cycle.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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D.J. Schepis et al., "A 0.25"m CMOS SOI technology and its application to 4 Mb SRAM," Proc. IEDM, Dec 1997, pp.587-590.
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R. V. Joshi et al., "A 666 MHz self-resetting 8 Port, 32x64 bits register "le and latch in 0.25"m SOI technology," Proc. 1998 IEEE Int. SOI Conf., Oct 1998, pp.131-132.
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W. H. Henkels, W. Hwang and R. V. Joshi, "A 500 MHz 32-Word x 64-Bit 8-Port Self-Resetting CMOS Register le and associated dynamic-to-static latch," VLSI Design Symp., June 1997, pp.41-42.
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Atila Alvandpour , Per Larsson-Edefors , Christer Svensson, Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits, Proceedings of the 1998 international symposium on Low power electronics and design, p.245-249, August 10-12, 1998, Monterey, California, United States
[doi> 10.1145/280756.280919]
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CITED BY
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J.-O. Plouchart , N. Zamdmer , J. Kim , M. Sherony , Y. Tan , A. Ray , M. Talbi , L. F. Wagner , K. Wu , N. E. Lustig , S. Narasimha , P. O'Neil , N. Phan , M. Rohn , J. Strom , D. M. Friend , S. V. Kosonocky , D. R. Knebel , S. Kim , K. A. Jenkins , M. Rivier, Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits, IBM Journal of Research and Development, v.47 n.5-6, p.611-629, September 2003
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