Speeding up power estimation of embedded software

ABSTRACT

Power is increasingly becoming a design constraint for embedded systems. A processor is responsible for energy consumption on account of the software component of the embedded system. The power estimation of this component is a major concern due to the rising complexities of processors and the slow estimation tools. This work attempts to estimate the energy dissipation of the PR1900 processor based on instruction set model with improved accuracy. The model is integrated in a simulation framework and validated. Over 200 times speedup has been obtained with average 1.4% loss in accuracy over gate level estimation. Analysis of the energy dissipated by the instruction vis a vis the processor architecture has been carried out and a substantial reduction in the measurement effort to build the processor energy model has been achieved.

REFERENCES

• 1: Guiseppe Bernacchia , Marios C. Papaefthymiou, Analytical macromodeling for high-level power estimation, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.280-283, November 07-11, 1999, San Jose, California, United States
• 2: Rita Yu Chen , Robert M. Owens , Mary Jane Irwin , R. S. Bajwa , Raminder S. Bajwa, Validation of an architectural level power analysis technique, Proceedings of the 35th annual conference on Design automation, p.242-245, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277106]
• 3: Subodh Gupta , Farid N. Najm, Power macromodeling for high level power estimation, Proceedings of the 34th annual conference on Design automation, p.365-370, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266171]
• 4: Gerry Kane, MIPS RISC architecture, Prentice-Hall, Inc., Upper Saddle River, NJ, 1988
• 5: Marcello Lajolo , Luciano Lavagno , Anand Raghunathan , Sujit Dey , Alberto Sangiovanni-Vincentelli, Efficient Power Estimation Techniques for HW/SW Systems, Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, p.191, March 04-05, 1999
• 6: P. L. Landman and J. M. Rabaey. Power estimation for high level synthesis. In Proc. of EDAC-EUROASIC'93, Paris, pages 361-366, February 1993.
• 7: P. L. Landman and J. M. Rabaey. Black box capacitance models for architectural power analysis. In Proceeding of international workshop on low power design, pages 165-170, April 1994.
• 8: Paul E. Landman , Jan M. Rabaey, Architectural power analysis: the dual bit type method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.173-187, June 1995 [doi>10.1109/92.386219]
• 9: Jing-Yuan Lin , Wen-Zen Shen , Jing-Yang Jou, A power modeling and characterization method for macrocells using structure information, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.502-506, November 09-13, 1997, San Jose, California, United States
• 10: Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin, Energy characterization based on clustering, Proceedings of the 33rd annual conference on Design automation, p.702-707, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240651]
• 11: Farid N. Najm, A survey of power estimation techniques in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.446-455, Dec. 1994 [doi>10.1109/92.335013]
• 12: Davide Sarta , Dario Trifone , Giuseppe Ascia, A Data Dependent Approach to Instruction Level Power Estimation, Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, p.182, March 04-05, 1999
• 13: Philips Semiconductors. PR1900 microprocessor RISC core user manual, v1.6. Philips Semiconductors, 1998.
• 14: Vivek Tiwari , Sharad Malik , Andrew Wolfe , Mike Tien-Chien Lee, Instruction level power analysis and optimization of software, Journal of VLSI Signal Processing Systems, v.13 n.2-3, p.223-238, Aug./Sept. 1996 [doi>10.1007/BF01130407]
• 15: Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.437-445, Dec. 1994 [doi>10.1109/92.335012]

INDEX TERMS

Primary Classification:
  D. Software
  D.4 OPERATING SYSTEMS

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

General Terms:
Design, Management, Theory