| A three-port nRERL register file for ultra-low-energy applications |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2000 international symposium on Low power electronics and design
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Rapallo, Italy
Pages: 161 - 166
Year of Publication: 2000
ISBN:1-58113-190-9
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Authors
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Jun-Ho Kwon
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School of Electrical Engineering, Seoul National University, Kwanak, P.O. Box 34, Seoul 151-742, Korea
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Joonho Lim
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Global Communication Technology, CA
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Soo-Ik Chae
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School of Electrical Engineering, Seoul National University, Kwanak, P.O. Box 34, Seoul 151-742, Korea
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Downloads (6 Weeks): 4, Downloads (12 Months): 22, Citation Count: 6
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ABSTRACT
In this paper, we propose an adiabatic register file for ultra-low-energy applications, which uses a new reversible adiabatic logic, nRERL [1]. The nRERL register file discards garbage information with minimal energy dissipation. We designed a 16x8b three-port nRERL register file. From SPICE simulations, we found that the nRERL register file consumes less than 10% of the energy consumed in the conventional register file at the frequency of lower than 1MHz. We also describe how to design a RAM, a large array of the storage cells
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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J. Lim, D. -G. Kim, and S. -I. Chae, "nMOS reversible energy recovery logic for ultra-low-energy applications," will be published in IEEE Journal of Solid-State Circuits, Jun. 2000.
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D. Somasekhar, Y. Ye, and K. Roy, "An energy recovery static RAM core, " in Proceeding of IEEE Symposium on Low Power Electronics, pp. 62-63, 1995.
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N. Tzartzanis , W. Athas, Energy recovery for the design of high-speed, low-power static RAMs, Proceedings of the 1996 international symposium on Low power electronics and design, p.55-60, August 12-14, 1996, Monterey, California, United States
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Y. Moon and D. -K. Jeong, "A 32x32-bit adiabatic register file with supply clock generator, " in Symposium on VLSI Circuits Dig. Tech. Papers, pp. 27-28, 1997.
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R. Merkle, "Reversible electronic logic using switches, " Nanotechnology, vol 4, pp. 21-40, 1993.
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C. J. Vieri, "Pendulum: a reversible computer architecture, " M.S. thesis, Massachusetts Institute of Technology, June 1995.
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C. Vieri, M. J. Ammer, A. Wakefield, L. "J. " Svensson, W. C. Athas, and T. Knight, "Designing reversible memory," in Proceeding of Unconventional Model of Computation, pp. 386-405, 1998.
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J. Lim, D. -G. Kim and S. -I. Chae, "A 16-b carry-lookahead adder using reversible energy recovery logic for ultra-lowenergy systems," IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 898-903, June 1999.
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J. Lim, K. Kwon and S. -I. Chae, "Reversible energy recovery logic circuit without non-adiabatic energy loss," lEE Electronics Letters, vol. 34, no. 4, pp. 344-346, Feb. 1998.
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J. Lim, D. -G. Kim and S. -I Chae, "Reversible energy recovery logic circuit and its 8-phase clocked power generator for ultra-low-power applications," IEICE Trans. on Electronics, vol. E82-C, no. 4, pp. 646-653, April 1999.
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J. Lim, D. -G. Kim and S. -I. Chae, "Reduction in energy consumption by bootstrapped nMOS switches in reversible adiabatic CMOS circuits," lEE Proceedings: Circuits, Devices, and Systems, vol. 146, No. 6, Dec. 1999.
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