High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies

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High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents

Rapallo, Italy

Pages: 155 - 160

Year of Publication: 2000

ISBN:1-58113-190-9

Authors

Mohamed W. Allam	VLSI Research Group, University of Waterloo, Waterloo, ON, Canada N2L 3G1
Mohab H. Anis	VLSI Research Group, University of Waterloo, Waterloo, ON, Canada N2L 3G1
Mohamed I. Elmasry	VLSI Research Group, University of Waterloo, Waterloo, ON, Canada N2L 3G1

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 13, Downloads (12 Months): 47, Citation Count: 18

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ABSTRACT

A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic power with minimal area overhead. A dual-threshold (MTCMOS) implementation of HS-Domino and DDCVS logic is also devised. This implementation achieves low leakage values during standby, while maintaining high performance and low dynamic power during the active mode.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 18

	Mohab H. Anis , Mohamed W. Allam , Mohamed I. Elmasry, Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.71-78, April 2002
	Farshad Moradi , Hamid Mahmoodi , Ali Peiravi, A high speed and leakage-tolerant domino logic for high fan-in gates, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Volkan Kursun , Eby G. Friedman, Low swing dual threshold voltage domino logic, Proceedings of the 12th ACM Great Lakes symposium on VLSI, April 18-19, 2002, New York, New York, USA
	Kwang-Il Oh , Lee-Sup Kim, A clock delayed sleep mode domino logic for wide dynamic OR gate, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Atila Alvandpour , Ram Krishnamurthy , K. Soumyanath , Shekhar Borkar, A low-leakage dynamic multi-ported register file in 0.13mm CMOS, Proceedings of the 2001 international symposium on Low power electronics and design, p.68-71, August 2001, Huntington Beach, California, United States
	Volkan Kursun , Eby G. Friedman, Sleep switch dual threshold voltage domino logic with reduced standby leakage current, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.5, p.485-496, May 2004
	Seongmoo Heo , Kenneth Barr , Mark Hampton , Krste Asanović, Dynamic fine-grain leakage reduction using leakage-biased bitlines, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Li Ding , Pinaki Mazumder, On circuit techniques to improve noise immunity of CMOS dynamic logic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.910-925, September 2004
	Walid Elgharbawy , Pradeep Golconda , Magdy Bayoumi, Noise-tolerant high fan-in dynamic CMOS circuit design, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Steven Dropsho , Volkan Kursun , David H. Albonesi , Sandhya Dwarkadas , Eby G. Friedman, Managing static leakage energy in microprocessor functional units, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Jun Yang , Jia Yu , Youtao Zhang, A low energy cache design for multimedia applications exploiting set access locality, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.10-11, p.653-664, October/November 2005
	Zhiyu Liu , Volkan Kursun, PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.12, p.1311-1319, December 2007
	Koji Fujii , Takakuni Douseki , Yuichi Kado, A sub-1V dual-threshold domino circuit using product-of-sum logic, Proceedings of the 2001 international symposium on Low power electronics and design, p.259-262, August 2001, Huntington Beach, California, United States
	W. Chen , W. Hwang , P. Kudva , G. Gristede , S. Kosonocky , R. Joshi, Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design, Proceedings of the 2001 international symposium on Low power electronics and design, p.263-266, August 2001, Huntington Beach, California, United States
	Zhiyu Liu , Volkan Kursun, Leakage current starved domino logic, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Amir Amirabadi , Ali Afzali-Kusha , Yousof Mortazavi , Mehrdad Nourani, Clock delayed domino logic with efficient variable threshold voltage keeper, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.2, p.125-134, February 2007
	Zhiyu Liu , Volkan Kursun, Leakage Biased Sleep Switch Domino Logic, Proceedings of the 7th International Symposium on Quality Electronic Design, p.318-323, March 27-29, 2006
	Keivan Navi , Mehrdad Maeen , Vahid Foroutan , Somayeh Timarchi , Omid Kavehei, A novel low-power full-adder cell for low voltage, Integration, the VLSI Journal, v.42 n.4, p.457-467, September, 2009