An improved pass transistor synthesis method for low power, high speed CMOS circuits

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An improved pass transistor synthesis method for low power, high speed CMOS circuits

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents

Rapallo, Italy

Pages: 120 - 124

Year of Publication: 2000

ISBN:1-58113-190-9

Authors

Tudor Vinereanu	National Microelectronics Research Centre, University College, Cork, Ireland
Sverre Lidholm	National Microelectronics Research Centre, University College, Cork, Ireland

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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Downloads (6 Weeks): 8, Downloads (12 Months): 29, Citation Count: 0

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ABSTRACT

A synthesis method for generating hybrid pass gate circuits is presented. These circuits combine features from both complementary CMOS and pass gates architectures. The simulation results using a 0.7 &mgr;m technology show that circuits synthesized according to the proposed method may achieve significant improvements in terms of area, power and delay over traditional full swing pass transistor logic and complementary CMOS.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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