MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments

ABSTRACT

In this work, MOS Current Mode Logic (MCML) is analyzed for application to low power, mixed signal environments. A small MCML cell library is developed and optimized for several different performance requirements. The cells are then applied to the generation of piplelined CORDIC structures and compared with equivalent CMOS circuits. MCML CORDICs are designed which can operate from 125MHz to 310MHz with power consumption varying between 4.3mW and 18.6mW. These power results are up to 1.5 times less than CMOS CORDICs with equivalent propagation delays. Design was done in a 0.25&mrg;m standard CMOS process from ST Microelectronics.

REFERENCES

• 1: [1] M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, H. Yamada, "A GHz MOS, Adaptive Pipeline Technique Using MOS Current-Mode Logic," IEEE Journal of Solid-State Circuits, Vol. 31, No. 6, June 1996, p. 784-791.
• 2: Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

General Terms:
Design, Management

Keywords:
CORDIC, current mode logic, digital logic, low-energy design