Voltage scheduling in the IpARM microprocessor system

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Voltage scheduling in the IpARM microprocessor system

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents

Rapallo, Italy

Pages: 96 - 101

Year of Publication: 2000

ISBN:1-58113-190-9

Authors

Trevor Pering	Berkeley Wireless Research Center, University of California, Berkeley, 2108 Allston Way, Berkeley, CA
Thomas Burd	Berkeley Wireless Research Center, University of California, Berkeley, 2108 Allston Way, Berkeley, CA
Robert Brodersen	Berkeley Wireless Research Center, University of California, Berkeley, 2108 Allston Way, Berkeley, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 34, Citation Count: 58

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

Microprocessors represent a significant portion of the energy conðsumed in portable electronic devices. Dynamic Voltage Scaling (DVS) allows a device to reduce energy consumption by lowering its processor speed at run-time, allowing a corresponding reduction in processor voltage and energy. A voltage scheduler determines the appropriate operating voltage by analyzing application conðstraints and requirements. A complete software implementation, including both applications and the underlying operating system, shows that DVS is effective at reducing the energy consumed withðout requiring extensive software modification.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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