Gated-Vdd

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Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents

Rapallo, Italy

Pages: 90 - 95

Year of Publication: 2000

ISBN:1-58113-190-9

Authors

Michael Powell	School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN
Se-Hyun Yang	School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN
Babak Falsafi	School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN
Kaushik Roy	School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN
T. N. Vijaykumar	School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 11, Downloads (12 Months): 80, Citation Count: 97

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ABSTRACT

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across appliðcations. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instrucðtion caches. We propose, gated-Vdd, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-Vdd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.

REFERENCES

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	1	David H. Albonesi, Selective cache ways: on-demand cache resource allocation, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.248-259, November 16-18, 1999, Haifa, Israel
	2	Nikolaos Bellas , Ibrahim Hajj , Constantine Polychronopoulos, Using dynamic cache management techniques to reduce energy in a high-performance processor, Proceedings of the 1999 international symposium on Low power electronics and design, p.64-69, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313856]
	3	Shekhar Borkar, Design Challenges of Technology Scaling, IEEE Micro, v.19 n.4, p.23-29, July 1999 [doi>10.1109/40.782564]
	4	D. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin--Madison, June 1997.
	5	Koji Inoue , Tohru Ishihara , Kazuaki Murakami, Way-predicting set-associative cache for high performance and low energy consumption, Proceedings of the 1999 international symposium on Low power electronics and design, p.273-275, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313948]
	6	Milind B. Kamble , Kanad Ghose, Analytical energy dissipation models for low-power caches, Proceedings of the 1997 international symposium on Low power electronics and design, p.143-148, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263310]
	7	Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	8	Srilatha Manne , Artur Klauser , Dirk Grunwald, Pipeline gating: speculation control for energy reduction, Proceedings of the 25th annual international symposium on Computer architecture, p.132-141, June 27-July 02, 1998, Barcelona, Spain
	9	Liqiong Wei , Zhanping Chen , Mark Johnson , Kaushik Roy , Vivek De, Design and optimization of low voltage high performance dual threshold CMOS circuits, Proceedings of the 35th annual conference on Design automation, p.489-494, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277179]
	10	S.J.E. Wilson and N. P. Jouppi. An enhanced access and cycle time model for on-chip caches. Technical Report 93/ 5, Digital Equipment Corporation, Western Research Laboratory, July 1994.
	11	S.-H. Yang, M. D. Powell, B. Falsafi, K. Roy, and T. N. Vijaykumar. Dynamically resizable instruction cache: An energy-efficient and high-performance deep-submicron instruction cache. Technical Report ECE-007, School of Electrical and Computer Engineering, Purdue University, 2000.
	12	Y. Ye, S. Borkar, and V. De. A new technique for standby leakage reduction in high performance circuits. In IEEE Symposium on VLSI Circuits, pages 40-41, 1998.

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	Stefanos Kaxiras , Zhigang Hu , Margaret Martonosi, Cache decay: exploiting generational behavior to reduce cache leakage power, ACM SIGARCH Computer Architecture News, v.29 n.2, p.240-251, May 2001
	J. Adam Butts , Gurindar S. Sohi, A static power model for architects, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.191-201, December 2000, Monterey, California, United States
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	Gokhan Memik , William H. Mangione-Smith, Increasing power efficiency of multi-core network processors through data filtering, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
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	I. Kadayif , M. Kandemir , N. Vijaykrishnan , M. J. Irwin , J. Ramanujam, Morphable Cache Architectures: Potential Benefits, ACM SIGPLAN Notices, v.36 n.8, p.128-137, Aug. 2001
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	Xuning Chen , Li-Shiuan Peh, Leakage power modeling and optimization in interconnection networks, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Heather Hanson , M. S. Hrishikesh , Vikas Agarwal , Stephen W. Keckler , Doug Burger, Static energy reduction techniques for microprocessor caches, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.303-313, June 2003
	Arindam Mukherjee , Malgorzata Marek-Sadowska, Clock and Power Gating with Timing Closure, IEEE Design & Test, v.20 n.3, p.32-39, May 2003
	Akihito Sakanaka , Seiichirou Fujii , Toshinori Sato, A leakage-energy-reduction technique for highly-associative caches in embedded systems, ACM SIGARCH Computer Architecture News, v.32 n.3, p.50-54, June 2004
	Krisztián Flautner , Nam Sung Kim , Steve Martin , David Blaauw , Trevor Mudge, Drowsy caches: simple techniques for reducing leakage power, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
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	Nam Sung Kim , Krisztián Flautner , David Blaauw , Trevor Mudge, Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi, Let caches decay: reducing leakage energy via exploitation of cache generational behavior, ACM Transactions on Computer Systems (TOCS), v.20 n.2, p.161-190, May 2002
	Arindam Mallik , Matthew C. Wildrick , Gokhan Memik, Design and implementation of correlating caches, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Narender Hanchate , Nagarajan Ranganathan, LECTOR: a technique for leakage reduction in CMOS circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.196-205, February 2004
	Hidenori Sato , Toshinori Sato, A static and dynamic energy reduction technique for I-cache and BTB in embedded processors, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.830-833, January 27-30, 2004, Yokohama, Japan
	Nam Sung Kim , Todd Austin , David Blaauw , Trevor Mudge , Krisztián Flautner , Jie S. Hu , Mary Jane Irwin , Mahmut Kandemir , Vijaykrishnan Narayanan, Leakage Current: Moore's Law Meets Static Power, Computer, v.36 n.12, p.68-75, December 2003
	Raksit Ashok , Saurabh Chheda , Csaba Andras Moritz, Coupling compiler-enabled and conventional memory accessing for energy efficiency, ACM Transactions on Computer Systems (TOCS), v.22 n.2, p.180-213, May 2004
	Benton H. Calhoun , Frank A. Honore , Anantha Chandrakasan, Design methodology for fine-grained leakage control in MTCMOS, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Michael Zhang , Krste Asanović, Fine-grain CAM-tag cache resizing using miss tags, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Zhigang Hu , Alper Buyuktosunoglu , Viji Srinivasan , Victor Zyuban , Hans Jacobson , Pradip Bose, Microarchitectural techniques for power gating of execution units, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
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	A. Gayasen , Y. Tsai , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , T. Tuan, Reducing leakage energy in FPGAs using region-constrained placement, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
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	Chuanjun Zhang , Jun Yang , Frank Vahid, Low Static-Power Frequent-Value Data Caches, Proceedings of the conference on Design, automation and test in Europe, p.10214, February 16-20, 2004
	Prasanth Mangalagiri , Karthik Sarpatwari , Aditya Yanamandra , VijayKrishnan Narayanan , Yuan Xie , Mary Jane Irwin , Osama Awadel Karim, A low-power phase change memory based hybrid cache architecture, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
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	Jaw-Wei Chi , Chia-Lin Yang , Yi-Jung Chen , Jien-Jia Chen, Cache leakage control mechanism for hard real-time systems, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
	Roberto Giorgi , Paolo Bennati, Reducing leakage in power-saving capable caches for embedded systems by using a filter cache, Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, p.97-104, September 16-16, 2007, Brasov, Romania
	Olga Golubeva , Mirko Loghi , Enrico Macii , Massimo Poncino, Locality-driven architectural cache sub-banking for leakage energy reduction, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Sung Woo Chung , Kevin Skadron, On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance, IEEE Transactions on Computers, v.57 n.1, p.7-24, January 2008
	Seiichiri Fujii , Akihito Sakanaka , Akihiro Chiyonobu , Toshinori Sato, A leakage-energy-reduction technique for cache memories in embedded processors, Journal of Embedded Computing, v.2 n.1, p.49-55, January 2006
	Maziar Goudarzi , Tohru Ishihara, Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
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	Behnam Amelifard , Farzan Fallah , Massoud Pedram, Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.851-860, July 2008
	Shengqi Yang , Wenping Wang , Tiehan Lu , Wayne Wolf , N. Vijaykrishnan , Yuan Xie, Case study of reliability-aware and low-power design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.861-873, July 2008
	Maziar Goudarzi , Tohru Ishihara , Hiroto Yasuura, A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation, Microelectronics Journal, v.39 n.12, p.1797-1808, December, 2008
	Abhishek Das , Berkin Ozisikyilmaz , Serkan Ozdemir , Gokhan Memik , Joseph Zambreno , Alok Choudhary, Evaluating the effects of cache redundancy on profit, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.388-398, November 08-12, 2008
	Hyunhee Kim , Sungjun Youn , Jihong Kim, A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches, Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, p.30-37, October 26-26, 2008, Toronto, Canada