Gated-Vdd

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Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents

Rapallo, Italy

Pages: 90 - 95

Year of Publication: 2000

ISBN:1-58113-190-9

Authors

Michael Powell	School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN
Se-Hyun Yang	School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN
Babak Falsafi	School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN
Kaushik Roy	School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN
T. N. Vijaykumar	School of Electrical and Computer Engineering, Purdue University, 1285 EE Building, West Lafayette, IN

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 16, Downloads (12 Months): 86, Citation Count: 97

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ABSTRACT

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across appliðcations. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instrucðtion caches. We propose, gated-Vdd, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-Vdd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.

REFERENCES

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