| Robust ultra-low power sub-threshold DTMOS logic |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2000 international symposium on Low power electronics and design
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Rapallo, Italy
Pages: 25 - 30
Year of Publication: 2000
ISBN:1-58113-190-9
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Authors
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Hendrawan Soeleman
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Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN
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Kaushik Roy
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Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN
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Bipul Paul
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Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN
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Downloads (6 Weeks): 6, Downloads (12 Months): 59, Citation Count: 5
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ABSTRACT
Digital sub-threshold logic circuits have recently been proposed for applications in the ultra-low power end of the design spectrum, where the performance is of secondary importance. To improve switching performance of the sub-threshold logic family with comparable energy/switching, we propose the use of sub-DTMOS (sub-threshold Dynamic Threshold MOS) transistors. The stability of sub-threshold DTMOS logic to temperature and process variations eliminates the need of additional stabilization scheme that may be required for regular sub-threshold MOS logic families to ensure proper operation in the sub-threshold region.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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A. Chandrakasan et.al., "Minimizing Power Consumption in Digital CMOS circuits", Proceedings of the IEEE, vol. 83, n. 4, April 1995.
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J. Rabaey et. al., editor, Low Power Design Methodologies, Kluwer Academic Publishers, 1996.
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T. Kobayashi and T. Sakurai, "Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation", in Custom Integrated Circuits Conference, pp. 271-274, May 1994.
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5
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T. Kuroda et. al., "A 0.9-V, 150-MHz, 10-mW, 4-mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme", IEEE Journal of Solid-State Circuits, vol. 31, n. 11, pp. 1770-1779, November 1996.
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6
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A. Sabnis and J. Clemens, "Characterization of the Electron Mobility in the Inverted < 100 > Si Surface", in Intl. Electron Devices Meeting, pp. 18-21, December 1979.
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F. Assaderaghi et. al., "A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation", in Intl. Electron Devices Meeting, pp. 809-812, 1994.
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H. Kotaki et. al., "Novel Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS", in Intl. Electron Devices Meeting, pp. 459-462, 1996.
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CITED BY 5
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Bo Zhai , David Blaauw , Dennis Sylvester , Krisztian Flautner, Theoretical and practical limits of dynamic voltage scaling, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
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