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Robust ultra-low power sub-threshold DTMOS logic
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents
Rapallo, Italy
Pages: 25 - 30  
Year of Publication: 2000
ISBN:1-58113-190-9
Authors
Hendrawan Soeleman  Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN
Kaushik Roy  Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN
Bipul Paul  Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 6,   Downloads (12 Months): 59,   Citation Count: 5
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ABSTRACT

Digital sub-threshold logic circuits have recently been proposed for applications in the ultra-low power end of the design spectrum, where the performance is of secondary importance. To improve switching performance of the sub-threshold logic family with comparable energy/switching, we propose the use of sub-DTMOS (sub-threshold Dynamic Threshold MOS) transistors. The stability of sub-threshold DTMOS logic to temperature and process variations eliminates the need of additional stabilization scheme that may be required for regular sub-threshold MOS logic families to ensure proper operation in the sub-threshold region.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
A. Chandrakasan et.al., "Minimizing Power Consumption in Digital CMOS circuits", Proceedings of the IEEE, vol. 83, n. 4, April 1995.
 
2
J. Rabaey et. al., editor, Low Power Design Methodologies, Kluwer Academic Publishers, 1996.
3
 
4
T. Kobayashi and T. Sakurai, "Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation", in Custom Integrated Circuits Conference, pp. 271-274, May 1994.
 
5
T. Kuroda et. al., "A 0.9-V, 150-MHz, 10-mW, 4-mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme", IEEE Journal of Solid-State Circuits, vol. 31, n. 11, pp. 1770-1779, November 1996.
 
6
A. Sabnis and J. Clemens, "Characterization of the Electron Mobility in the Inverted < 100 > Si Surface", in Intl. Electron Devices Meeting, pp. 18-21, December 1979.
 
7
F. Assaderaghi et. al., "A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation", in Intl. Electron Devices Meeting, pp. 809-812, 1994.
 
8
H. Kotaki et. al., "Novel Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS", in Intl. Electron Devices Meeting, pp. 459-462, 1996.


Collaborative Colleagues:
Hendrawan Soeleman: colleagues
Kaushik Roy: colleagues
Bipul Paul: colleagues