Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation

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Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents

Rapallo, Italy

Pages: 15 - 19

Year of Publication: 2000

ISBN:1-58113-190-9

Authors

Fatih Hamzaoglu	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
Yibin Te	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
Ali Keshavarzi	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
Kevin Zhang	Low Power Design Lab, Intel Corporation, Hillsboro, OR
Siva Narendra	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
Shekhar Borkar	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
Mircea Stan	Department of ECE, University of Virginia, Charlottesville, VA
Vivek De	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 51, Citation Count: 13

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ABSTRACT

Comparisons among different dual-VT design choices for a large on-chip cache with single-ended sensing show that the design using a dual-VT cell and low-VT peripheral circuits is the best, and provides 10% performance gain with 1.2x larger active leakage power, and 1.6% larger cell area compared to the best design using high-VT cells.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	V. De, S. Borkar, Proc. ISLPED 99, pp. 163-168
	2	S. Thompson et al., 1997 Symp. on VLSI Tech., pp. 69-70
	3	N. Rohrer et al., IEEE ISSCC 98, pp. 240-241
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	6	I. Fukushi et al., 1998 Symp. on VLSI Ckt., pp. 142-145
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CITED BY 13

	Navid Azizi , Andreas Moshovos , Farid N. Najm, Low-leakage asymmetric-cell SRAM, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Amit Agarwal , Hai Li , Kaushik Roy, DRG-cache: a data retention gated-ground cache for low power, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Navid Azizi , Farid N. Najm , Andreas Moshovos, Low-leakage asymmetric-cell SRAM, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.701-715, August 2003
	Sung-Mo Kang, Elements of low power design for integrated systems, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Robert K. Grube , Qi Wang , Sung-Mo Kang, Design limitations in deep sub-0.1&mgr;m CMOS SRAM, Proceedings of the 12th ACM Great Lakes symposium on VLSI, April 18-19, 2002, New York, New York, USA
	Seongmoo Heo , Kenneth Barr , Mark Hampton , Krste Asanović, Dynamic fine-grain leakage reduction using leakage-biased bitlines, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Shengqi Yang , Wayne Wolf , Wenping Wang , N. Vijaykrishnan , Yuan Xie, Low-leakage robust SRAM cell design for sub-100nm technologies, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Andreas Moshovos , Babak Falsafi , Farid N. Najm , Navid Azizi, A case for asymmetric-cell cache memories, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.7, p.877-881, July 2005
	Richard F. Hobson, A new single-ended SRAM cell with write-assist, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.2, p.173-181, February 2007
	Behnam Amelifard , Massoud Pedram , Farzan Fallah, Low-leakage SRAM Design with Dual V_t Transistors, Proceedings of the 7th International Symposium on Quality Electronic Design, p.729-734, March 27-29, 2006
	Hamed F. Dadgour , Kaustav Banerjee, Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Behnam Amelifard , Farzan Fallah , Massoud Pedram, Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.851-860, July 2008
	Shengqi Yang , Wenping Wang , Tiehan Lu , Wayne Wolf , N. Vijaykrishnan , Yuan Xie, Case study of reliability-aware and low-power design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.861-873, July 2008