Automating RT-level operand isolation to minimize power consumption in datapaths

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Automating RT-level operand isolation to minimize power consumption in datapaths

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 624 - 633

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

M. Münch	University of Kaiserslautern, Erwin-Schroedinger-Strasse, D-67663 Kaiserslautern, Germany
B. Wurth	Infineon Technologies AG, P.O. Box 800949, D-81609, Munich
R. Mehra	Synopsys, Inc., 700 East Middlefield Rd., Mountain View, CA
J. Sproch	Synopsys, Inc., 700 East Middlefield Rd., Mountain View, CA
N. Wehn	University of Kaiserslautern, Erwin-Schroedinger-Strasse, D-67663 Kaiserslautern, Germany

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 26, Citation Count: 13

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. IEEE Press, 1990.
	2	Anantha P. Chandrakasan , Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Norwell, MA, 1995
	3	Anthony Correale, Jr., Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers, Proceedings of the 1995 international symposium on Low power design, p.75-80, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224095]
	4	H. Kapadia, L. Benini, and G. D. Micheli. Reducing Switching Activity on Datapath Buses with Control-Signal Gating. IEEE Journal of Solid-State Circuits, 34(3):405-414, Mar. 1999.
	5	Paul Eric Landman, Low-power architectural design methodologies, University of California at Berkeley, Berkeley, CA, 1995
	6	M. Mtinch. Synthesis and Optimization of Algorithmic Hardware Descriptions. PhD thesis, University of Kaiserslautern, 1999.
	7	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996 [doi>10.1145/225871.225877]
	8	Synopsys, Inc., Mountain View, CA. Synopsys Power Products Reference Manual, v1997.08 edition, 1997.
	9	V. Tiwari, S. Malik, and R Ashar. Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 17(10):1051-1060, Oct. 1998.

CITED BY 13

	Monica Donno , Alessandro Ivaldi , Luca Benini , Enrico Macii, Clock-tree power optimization based on RTL clock-gating, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Luca Benini , Giovanni De Micheli, Logic synthesis for low power, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Shanq-Jang Ruan , Kun-Lin Tsai , Edwin Naroska , Feipei Lai, Bipartitioning and encoding in low-power pipelined circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.24-32, January 2005
	Lin Zhong , Niraj K. Jha, Interconnect-aware high-level synthesis for low power, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.110-117, November 10-14, 2002, San Jose, California
	Monica Donno , Enrico Macii , Luca Mazzoni, Power-aware clock tree planning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	M. Müller , S. Simon , H. Gryska , A. Wortmann , S. Buch, Low power synthesizable register files for processor and IP cores, Integration, the VLSI Journal, v.39 n.2, p.131-155, March 2006
	Pietro Babighian , Luca Benini , Enrico Macii, A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks, Proceedings of the conference on Design, automation and test in Europe, p.10500, February 16-20, 2004
	A. Chattopadhyay , B. Geukes , D. Kammler , E. M. Witte , O. Schliebusch , H. Ishebabi , R. Leupers , G. Ascheid , H. Meyr, Automatic ADL-based operand isolation for embedded processors, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	N. Banerjee , A. Raychowdhury , K. Roy , S. Bhunia , H. Mahmoodi, Novel low-overhead operand isolation techniques for low-power datapath synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.9, p.1034-1039, September 2006
	Pietro Babighian , Gila Kamhi , Moshe Vardi, Interactive presentation: PowerQuest: trace driven data mining for power optimization, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Hirofumi Iwato , Keishi Sakanushi , Yoshinori Takeuchi , Masaharu Imai, A low power VLIW processor generation method by means of extracting non-redundant activation conditions, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria
	Qi Wang , Sumit Roy, RTL Power Optimization with Gate-Level Accuracy, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.39, November 09-13, 2003
	Yu-Min Kuo , Shih-Hung Weng , Shih-Chieh Chang, A novel sequential circuit optimization with clock gating logic, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California