Cost reduction and evaluation of temporary faults detecting technique

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Cost reduction and evaluation of temporary faults detecting technique

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 591 - 598

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Lorena Anghel	TIMA, France
Michael Nicolaidis	TIMA, France

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 7, Downloads (12 Months): 13, Citation Count: 25

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 26

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	Eric Dupont , Michael Nicolaidis , Peter Rohr, Embedded Robustness IPs for Transient-Error-Free ICs, IEEE Design & Test, v.19 n.3, p.56-70, May 2002
	Rodrigo Possamai Bastos , Fernanda Lima Kastensmidt , Ricardo Reis, Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates, Proceedings of the 19th annual symposium on Integrated circuits and systems design, August 28-September 01, 2006, Ouro Preto, MG, Brazil
	Fernanda Lima , Luigi Carro , Ricardo Reis, Designing fault tolerant systems into SRAM-based FPGAs, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Jongman Kim , Dongkook Park , Chrysostomos Nicopoulos , N. Vijaykrishnan , Chita R. Das, Design and analysis of an NoC architecture from performance, reliability and energy perspective, Proceedings of the 2005 symposium on Architecture for networking and communications systems, October 26-28, 2005, Princeton, NJ, USA
	Dan Alexandrescu , Lorena Anghel , Michael Nicolaidis, Simulating Single Event Transients in VDSM ICs for Ground Level Radiation, Journal of Electronic Testing: Theory and Applications, v.20 n.4, p.413-421, August 2004
	Chong Zhao , Xiaoliang Bai , Sujit Dey, A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	S. Matakias , Y. Tsiatouhas , A. Arapoyanni , Th. Haniotakis, A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs, Journal of Electronic Testing: Theory and Applications, v.20 n.5, p.523-531, October 2004
	M. Sonza Reorda , M. Violante, Efficient analysis of single event transients, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.5, p.239-246, April 2004
	Yi Zhao , Sujit Dey , Li Chen, Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.746-755, July 2004
	C. A. L. Lisbôa , E. Schüler , Luigi Carro, Going beyond TMR for protection against multiple faults, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
	M. Sonza Reorda , M. Violante, A New Approach to the Analysis of Single Event Transients in VLSI Circuits, Journal of Electronic Testing: Theory and Applications, v.20 n.5, p.511-521, October 2004
	Chong Zhao , Sujit Dey , Xiaoliang Bai, Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits, IEEE Design & Test, v.22 n.4, p.362-375, July 2005
	Chong Zhao , Yi Zhao , Sujit Dey, Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Robert Baumann, Soft Errors in Advanced Computer Systems, IEEE Design & Test, v.22 n.3, p.258-266, May 2005
	Shanq-Jang Ruan , Edwin Naroska , Chun-Chih Chen, Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Balkaran S. Gill , Chris Papachristou , Francis G. Wolff, Soft delay error analysis in logic circuits, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Arindam Mallik , Gokhan Memik, A Case for Clumsy Packet Processors, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.147-156, December 04-08, 2004, Portland, Oregon
	Lorenzo Petroli , Carlos A. Lisboa , Fernanda L. Kastensmidt , Luigi Carro, Using majority logic to cope with long duration transient faults, Proceedings of the 20th annual conference on Integrated circuits and systems design, September 03-06, 2007, Copacabana, Rio de Janeiro
	Balkaran S. Gill , Chris Papachristou , Francis G. Wolff, Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Chong Zhao , Sujit Dey, Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO), Proceedings of the 7th International Symposium on Quality Electronic Design, p.133-140, March 27-29, 2006
	I.-C. Lin , S. Srinivasan , N. Vijaykrishnan , N. Dhanwada, Transaction Level Error Susceptibility Model for Bus Based SoC Architectures, Proceedings of the 7th International Symposium on Quality Electronic Design, p.775-780, March 27-29, 2006
	Balkaran Gill , Michael Nicolaidis , Francis Wolff , Chris Papachristou , Steven Garverick, An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories, Proceedings of the conference on Design, Automation and Test in Europe, p.592-597, March 07-11, 2005
	Carlos A. L. Lisboa , Fernanda G. L. Kastensmidt , Luigi Carro, Analyzing the effects of the granularity of recomputation based techniques to cope with radiation induced soft errors, Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies, p.329-338, May 05-07, 2008, Ischia, Italy
	Chong Zhao , Yi Zhao , Sujit Dey, Intelligent robustness insertion for optimal transient error tolerance improvement in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.714-724, June 2008
	Rodrigo Possamai Bastos , Fernanda Lima Kastensmidt , Ricardo Reis, Design of a soft-error robust microprocessor, Microelectronics Journal, v.40 n.7, p.1062-1068, July, 2009