Standards for system-level design

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Standards for system-level design: practical reality or solution in search of a question?

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 576 - 585

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Christopher K. Lennard	Cadence
Patrick Schaumont	IMEC
Gjalt de Jong	Alcatel
Anssi Haverinen	Nokia
Pete Hardee	CoWare

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 6, Citation Count: 15

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	VSIA, VSI Alliance Architecture Document vl.O, www.vsi.org, March 1997
	2	VSIA, VSIA System Level Design Model Taxonomy Document, www.vsi.org, Jan 1999
	3	R. Goering, VSI spec establishes system-modeling taxonomy, EE Times, Feb 1999
	4	James A. Rowson , Alberto Sangiovanni-Vincentelli, Interface-based design, Proceedings of the 34th annual conference on Design automation, p.178-183, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266060]
	5	C. Lennard, Enabling VC Exchange through System-Level VC Standards, Proc. of Forum on Design Languages, pp. 641-650, Sept 1999
	6	K.Suzuki, et al, OwL: An Interface Description Language for IP Reuse, in Proc. of Custom Integrated Circuits Conference, pp.403-406, May 1999.
	7	Ptolemy II Heterogeneous Concurrent Modeling and Design in Java vO.l.1, ERL Technical Report, University of California Berkeley, Feb 1999
	8	IEEE Std 1164-1993 IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_l 164)
	9	IEEE Std 1076.3-1997 IEEE Standard VHDL Synthesis Packages

CITED BY 15

	A. Baghdadi , D. Lyonnard , N. Zergainoh , A. Jerraya, An efficient architecture model for systematic design of application-specific multiprocessor SoC, Proceedings of the conference on Design, automation and test in Europe, p.55-63, March 2001, Munich, Germany
	Damien Lyonnard , Sungjoo Yoo , Amer Baghdadi , Ahmed A. Jerraya, Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip, Proceedings of the 38th conference on Design automation, p.518-523, June 2001, Las Vegas, Nevada, United States
	Sungjoo Yoo , Gabriela Nicolescu , Damien Lyonnard , Amer Baghdadi , Ahmed A. Jerraya, A generic wrapper architecture for multi-processor SoC cosimulation and design, Proceedings of the ninth international symposium on Hardware/software codesign, p.195-200, April 2001, Copenhagen, Denmark
	Diederik Verkest , Joachim Kunkel , Frank Schirrmeister, System level design using C++, Proceedings of the conference on Design, automation and test in Europe, p.74-83, March 27-30, 2000, Paris, France
	Abhijit K. Deb , Johnny Öberg , Axel Jantsch, Control and communication performance analysis of embedded DSP systems in the MASIC methodology, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Ferid Gharsalli , Samy Meftali , Frédéric Rousseau , Ahmed A. Jerraya, Automatic generation of embedded memory wrapper for multiprocessor SoC, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Gabriela Nicolescu , Sungjoo Yoo , Aimen Bouchhima , Ahmed Amine Jerraya, Validation in a component-based design flow for multicore SoCs, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	G. Nicolescu , S. Yoo , A. Jerraya, Mixed-level cosimulation for fine gradual refinement of communication in SoC design, Proceedings of the conference on Design, automation and test in Europe, p.754-759, March 2001, Munich, Germany
	Giovanni Agosta , Francesco Bruschi , Donatella Sciuto, Static analysis of transaction-level models, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Férid Gharsalli , Damien Lyonnard , Samy Meftali , Frédéric Rousseau , Ahmed A. Jerraya, Unifying memory and processor wrapper architecture in multiprocessor SoC design, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	W. Cesário , L. Gauthier , D. Lyonnard , G. Nicolescu , A. A. Jerraya, Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits, Journal of Systems and Software, v.70 n.3, p.229-244, March 2004
	Miljan Vuletić , Laura Pozzi , Paolo Ienne, Virtual memory window for application-specific reconfigurable coprocessors, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Abhijit K. Deb , Axel Jantsch , Johnny Öberg, System design for DSP applications in transaction level modeling paradigm, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Miljan Vuleti , Ludovic Righetti , Laura Pozzi , Paolo Ienne, Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors, Proceedings of the conference on Design, automation and test in Europe, p.10748, February 16-20, 2004
	Robertas Damaševičius , Vytautas Štuikys, Wrapping of Soft IPs for Interface-based Design Using Heterogeneous Metaprogramming, Informatica, v.14 n.1, p.3-18, January 2003