Static timing analysis of embedded software on advanced processor architectures

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Static timing analysis of embedded software on advanced processor architectures

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 552 - 559

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

A. Hergenhan	Forschungszentrum Informatik (FZI), Haid-und-Neu-Str 10-14, 76131 Karlsruhe, Germany and Universität Tübingen, Sand 13, 72076 Tübingen, Germany
W. Rosenstiel	Universität Tübingen, Sand 13, 72076 Tübingen, Germany

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 23, Citation Count: 15

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Ernst , W. Ye, Embedded program timing analysis based on path clustering and architecture classification, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.598-604, November 09-13, 1997, San Jose, California, United States
	2	C. Ferdinand and R. Wilhelm. Fast and Efficient Cache Behavior Prediction. 10-page-handout, Universitfit des Saarlandes, Sept. 1997.
	3	Somnath Ghosh , Margaret Martonosi , Sharad Malik, Cache miss equations: an analytical representation of cache misses, Proceedings of the 11th international conference on Supercomputing, p.317-324, July 07-11, 1997, Vienna, Austria [doi>10.1145/263580.263657]
	4	Y.-T. S. Li , S. Malik , A. Wolfe, Cache modeling for real-time software: beyond direct mapped instruction caches, Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), p.254, December 04-06, 1996
	5	S.-S. Lim , J. H. Han , J. Kim , S. L. Min, A Worst Case Timing Analysis Technique for Multiple-Issue Machines, Proceedings of the IEEE Real-Time Systems Symposium, p.334, December 02-04, 1998
	6	S. Lim, B. Rhee, H. Shin, Y. Bae, S. Min, K. Park, and G. Jang. An Accurate Worst Case Timing Analysis Technique for RISC Processors. In Proceedings of the 16th IEEE Real-Time Systems Symposium, pages 97-108, December 1995.
	7	Motorola Computer Group, Motorola Inc. User Manual's CPX2108 CompactPCI System. http://www.mcg.mot.com/, 1999.
	8	Chang Yun Park, Predicting deterministic execution times of real-time programs, University of Washington, Seattle, WA, 1992
	9	P. Puschner , Ch. Koza, Calculating the maximum, execution time of real-time programs, Real-Time Systems, v.1 n.2, p.159-176, Sep. 1989 [doi>10.1007/BF00571421]
	10	A. Siebenborn. Cache-Modellierung fiir die statische Laufzeitanalyse von Software auf eingebetteten Mikrocontrollern. Diploma Thesis, Universitfit Karlsruhe, 1999.
	11	J. Teich. Digitale Hardware/Software-Systeme. Springer- Verlag, Berlin, Heidelberg, New York, 1997.
	12	K. Weiss, T. Steckstor, C. Oetker, and R. Kistner. User Manual SPYDER-CORE-P1. http://www.fzi.de/sim/spyder.html, 1998.

CITED BY 15

	Fabian Wolf , Jan Staschulat , Rolf Ernst, Associative caches in formal software timing analysis, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	G. Beltrame , C. Brandolese , W. Fornaciari , F. Salice , D. Sciuto , V. Trianni, Modeling assembly instruction timing in superscalar architectures, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	Márcio Seiji Oyamada , Felipe Zschornack , Flávio Rech Wagner, Accurate software performance estimation using domain classification and neural networks, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
	Kai Richter , Dirk Ziegenbein , Marek Jersak , Rolf Ernst, Model composition for scheduling analysis in platform design, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	A. Siebenborn , O. Bringmann , W. Rosenstiel, Worst-case performance analysis of parallel, communicating software processes, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Fabian Wolf , Rolf Ernst , Wei Ye, Path clustering in software timing analysis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.773-782, 12/1/2001
	Alexander Viehl , Timo Schönwald , Oliver Bringmann , Wolfgang Rosenstiel, Formal performance analysis and simulation of UML/SysML models for ESL design, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	James J. Hunt , Fridtjof B. Siebert , Peter H. Schmitt , Isabel Tonin, Provably correct loops bounds for realtime Java programs, Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems, October 11-13, 2006, Paris, France
	Jan Reineke , Daniel Grund, Relative competitiveness of cache replacement policies, ACM SIGMETRICS Performance Evaluation Review, v.36 n.1, June 2008
	A. Siebenborn , O. Bringmann , W. Rosenstiel, Communication Analysis for System-On-Chip Design, Proceedings of the conference on Design, automation and test in Europe, p.10648, February 16-20, 2004
	H. Posadas , F. Herrera , P. Sánchez , E. Villar , F. Blasco, System-Level Performance Analysis in SystemC, Proceedings of the conference on Design, automation and test in Europe, p.10378, February 16-20, 2004
	Jan Reineke , Daniel Grund, Relative competitive analysis of cache replacement policies, ACM SIGPLAN Notices, v.43 n.7, July 2008
	Marcio Seiji Oyamada , Felipe Zschornack , Flávio Rech Wagner, Applying neural networks to performance estimation of embedded software, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.1-2, p.224-240, January, 2008
	James J. Hunt , Isabel Tonin , Fridtjof B. Siebert, Using global data flow analysis on bytecode to aid worst case execution time analysis for real-time Java programs, Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems, September 24-26, 2008, Santa Clara, California
	Jinho Suh , Michel Dubois, Dynamic MIPS rate stabilization in out-of-order processors, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009