Clocktree RLC extraction with efficient inductance modeling

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Clocktree RLC extraction with efficient inductance modeling

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 522 - 526

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Norman Chang	Hewlett-Packard Laboratories, Palo Alto, CA
Shen Lin	Hewlett-Packard Laboratories, Palo Alto, CA
Lei He	ECE Dept., University of Wisconsin, Madison, WI
O. Sam Nakagawa	Hewlett-Packard Laboratories, Palo Alto, CA
Weize Xie	Hewlett-Packard Laboratories, Palo Alto, CA

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 6, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Shen Lin , John P. Lillis, Interconnect Analysis and Synthesis, John Wiley & Sons, Inc., New York, NY, 1999
	2	Shannon V. Morton, On-chip inductance issues in multiconductor systems, Proceedings of the 36th ACM/IEEE conference on Design automation, p.921-926, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310099]
	3	Phillip Restle , Albert Ruehli , Steven G. Walker, Dealing with inductance in high-speed chip design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.904-909, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310096]
	4	N. Chang, V. Kanevsky, O. S. Nakagawa, K. Rahmat, and S.-Y. Oh, "Fast Generation of Statistically-based Worst- Case Modeling of On-Chip Interconnect", IEEE ICCD 1997.
	5	L. He, N. Chang, S. Lin, and O. S. Nakakawa, "Efficient Inductance Modeling for On-chip Interconnects", IEEE CICC, 1999.
	6	Raphael User Manual, Avant! Corporation
	7	A.E. Ruehli, "Inductance Calculation in a Complex Integrated Circuit Environment," IBM Journal of Res. & Dev., 1972.
	8	A.E. Ruehli, "Equivalent Circuit Models for Three- Dimensional Multiconductor Systems," IEEE Trans. on MIT, 1974.
	9	M. Kamon, M.J. Tsuk, J. White, "Fasthenry: a Multipole- Accelerated 3D Inductance Extraction Program," IEEE Trans. on MIT, 1994.
	10	William H. Press , Saul A. Teukolsky , William T. Vetterling , Brian P. Flannery, Numerical recipes in C (2nd ed.): the art of scientific computing, Cambridge University Press, New York, NY, 1992
	11	Kerry Bernstein , Keith M. Carrig , Christopher M. Durham , Patrick R. Hansen , David Hogenmiller , Edward J. Nowak , Norman J. Rohrer, High speed CMOS design styles, Kluwer Academic Publishers, Norwell, MA, 1998

CITED BY 4

	Kaustav Banerjee , Amit Mehrotra, Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects, Proceedings of the 38th conference on Design automation, p.798-803, June 2001, Las Vegas, Nevada, United States
	Min Xu , Lei He, An efficient model for frequency-dependent on-chip inductance, Proceedings of the 11th Great Lakes symposium on VLSI, p.115-120, March 2001, West Lafayette, Indiana, United States
	Jun Chen , Lei He, Modeling of coplanar waveguide for buffered clock tree, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.367-372, January 27-30, 2004, Yokohama, Japan
	Tao Lin , Michael W. Beattie , Lawrence T. Pileggi, On the efficacy of simplified 2D on-chip inductance models, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA