Static timing analysis taking crosstallk into account

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Static timing analysis taking crosstallk into account

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 451 - 457

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Mattias Ringe	IBM Deutschland Entwicklung GmbH, Schönaicher Str. 220, 71032 Böblingen, Germany
Thomas Lindenkreuz	Robert Bosch GmbH, 72703 Reutlingen, Germany
Erich Barke	Institute of Microelectronic Systems, University of Hanover, 30167 Hanover, Germany

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 10, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Tilmann Stöhr , Markus Alt , Asmus Hetzel , Jürgen Koehl, Analysis, reduction and avoidance of crosstalk on VLSI chips, Proceedings of the 1998 international symposium on Physical design, p.211-218, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274566]
	2	A. Rubio, N Itazaki, X. Xu, K. Kinoshita, "An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits", IEEE T. o. CAD, Vol. 13, No. 3, pp. 387- 395, 1994
	3	Florentin Dartu , Lawrence T. Pileggi, Calculating worst-case gate delays due to dominant capacitance coupling, Proceedings of the 34th annual conference on Design automation, p.46-51, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266033]
	4	Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
	5	J. Koehl , U. Baur , T. Ludwig , B. Kick , T. Pflueger, A flat, timing-driven design system for a high-performance CMOS processor chipset, Proceedings of the conference on Design, automation and test in Europe, p.312-320, February 23-26, 1998, Le Palais des Congrés de Paris, France
	6	Florentin Dartu , Lawrence T. Pileggi, TETA: transistor-level engine for timing analysis, Proceedings of the 35th annual conference on Design automation, p.595-598, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277200]
	7	N.P. Jouppi, "Timing Analysis and Performance Improvement of MOS VLSI Designs", IEEE T. o. CAD, Vol. 6, No. 4, pp. 650-665, 1987
	8	T.G. Szymanski, "LEADOUT: A Static Timing Analyzer for MOS Circuits", ICCAD-86 Digest of Technical Papers, pp. 130-133, 1986
	9	David E. Wallace , Carlo H. Séquin, ATV: an abstract timing verifier, Proceedings of the 25th ACM/IEEE conference on Design automation, p.154-159, June 12-15, 1988, Atlantic City, New Jersey, United States
	10	J.K. Ousterhout, "A Switch-Level Timing Verifier for Digital MOS VLSI" IEEE T. o. CAD, Vol. 4, No. 3, pp. 336- 349, 1985
	11	J. Benkoski, E. Meersch, L. Claesen, H. de Man, "Efficient algorithms for solving the false path problem in timing verification", ICCAD-87 Digest of Technical Papers, pp. 44- 47, 1987.

CITED BY 2

	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Sung-Mo Kang, Minimum delay optimization for domino logic circuits---a coupling-aware approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.203-213, April 2003
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003