| Meeting delay constraints in DSM by minimal repeater insertion |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe
table of contents
Paris, France
Pages: 436 - 440
Year of Publication: 2000
ISBN:1-58113-244-1
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Authors
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I-Min Liu
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Department of Electrical and Computer Engineering, The University of Texas at Austin
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Adnan Aziz
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Department of Electrical and Computer Engineering, The University of Texas at Austin
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D. F. Wong
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Department of Computer Sciences, The University of Texas at Austin
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Downloads (6 Weeks): 3, Downloads (12 Months): 8, Citation Count: 8
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[doi> 10.1145/309847.309983]
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John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin, Optimal wire sizing and buffer insertion for low power and a generalized delay model, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.138-143, November 05-09, 1995, San Jose, California, United States
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I.-M. Liu, A. Aziz, D. F. Wong, and H. Zhou. An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. In Proc. Intl. Conf. on Computer Design, pages 614-621, 1999.
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L. P. P. P. van Ginneken. Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay. In Proc. Intl. Symposium on Circuits and Systems, pages 865-868, 1990.
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Hai Zhou , D. F. Wong , I-Min Liu , Adnan Aziz, Simultaneous routing and buffer insertion with restrictions on buffer locations, Proceedings of the 36th ACM/IEEE conference on Design automation, p.96-99, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.309885]
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CITED BY 8
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C. N. Sze , Charles J. Alpert , Jiang Hu , Weiping Shi, Path based buffer insertion, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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