Fast cache and bus power estimation for parameterized system-on-a-chip design

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Fast cache and bus power estimation for parameterized system-on-a-chip design

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 333 - 339

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Tony D. Givargis	Department of Computer Science and Engineering, University of California, Riverside, CA
Frank Vahid	Department of Computer Science and Engineering, University of California, Riverside, CA
Jörg Henkel	C&C Research Laboratories, NEC, 4 Independence Way, Princeton, NJ

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

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ACM New York, NY, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 12, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 2

	A. Bakshi , V. K. Prasanna , A. Ledeczi, MILAN: A Model Based Integrated Simulation Framework for Design of Embedded Systems, ACM SIGPLAN Notices, v.36 n.8, p.82-93, Aug. 2001
	Maurizio Palesi , Tony Givargis, Multi-objective design space exploration using genetic algorithms, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado