Gate sizing using a statistical delay model

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Gate sizing using a statistical delay model

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 283 - 291

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

E. T. A. F. Jacobs	Design Automation Section, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, The Netherlands
M. R. C. M. Berkelaar	Design Automation Section, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, The Netherlands

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 30, Citation Count: 26

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Berkelaar, M.R.C.M., 'Statistical Delay Calculation', Workshop Notes of the International Workshop on Logic Synthesis, May 18-21, 1997
	2	Berkelaar, M.R.C.M., 'Statistical Delay Calculation, a Linear Time Method', Proceedings of TAU'97, Austin, TX, December 4-5, 1997, pp. 15-24.
	3	Michel R. C. M. Berkelaar , Jochen A. G. Jess, Gate sizing in MOS digital circuits with linear programming, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	4	Brayton, R.K., R. Rudell, A.L. Sangiovanni-Vincentelli and A. Wang, 'MIS: A Multiple-Level Logic Optimization System', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov. 1987, Vol. CAD-6, pp. 1062-1081.
	5	A. R. Conn , N. I. M. Gould , Ph L. Toint, Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A), Springer-Verlag New York, Inc., Secaucus, NJ, 1992
	6	Robert B. Hitchcock, Sr., Timing Verification and the Timing Analysis program, Proceedings of the 19th conference on Design automation, p.594-604, January 1982
	7	Hitchcock, R.B., G.L. Smith, D.D. Cheng, 'Timing Analysis of Computer Hardware', IBM Journal of Research and Development, Vol. 26 No. 1, January 1982, pp. 100-105.
	8	Jacobs, E.T.A.F., 'Using Gate Sizing to Reduce Glitch Power', Proceedings of the Prorisc/IEEE Workshop on Circuits, Systems and Signal Processing, Mierlo, The Netherlands, November 27-28, 1996, pp. 183-188.
	9	Jyu, H.H., 'Statistical Delay Model Based Performance Analysis and Optimization in Logic Circuit Design', Ph.D. Thesis, Princeton University, 1994.
	10	Papoulis, A., 'Probability, Random Variables, and Stochastic Processes', Third Edition, McGraw-Hill New York, ISBN 0-07-048477-5, 1991.

CITED BY 26

	Yuji Kukimoto , Michel Berkelaar , Karem Sakallah, Static timing analysis, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Shuji Tsukiyama , Masakazu Tanaka , Masahiro Fukui, A statistical static timing analysis considering correlations between delays, Proceedings of the 2001 conference on Asia South Pacific design automation, p.353-358, January 2001, Yokohama, Japan
	Seung Hoon Choi , Bipul C. Paul , Kaushik Roy, Novel sizing algorithm for yield improvement under process variation in nanometer technology, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Masanori Hashimoto , Hidetoshi Onodera, A performance optimization method by gate sizing using statistical static timing analysis, Proceedings of the 2000 international symposium on Physical design, p.111-116, May 2000, San Diego, California, United States
	J. Dambre , D. Stroobandt , J. Van Campenhout, A probabilistic approach to clock cycle prediction, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Shuji Tsukiyama, Toward stochastic design for digital circuits: statistical static timing analysis, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.762-767, January 27-30, 2004, Yokohama, Japan
	Jaskirat Singh , Vidyasagar Nookala , Zhi-Quan Luo , Sachin Sapatnekar, Robust gate sizing by geometric programming, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Aseem Agarwal , Kaviraj Chopra , David Blaauw , Vladimir Zolotov, Circuit optimization using statistical static timing analysis, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Murari Mani , Anirudh Devgan , Michael Orshansky, An efficient algorithm for statistical minimization of total power under timing yield constraints, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Kai-Chiang Wu , Cheng-Tao Hsieh , Shih-Chieh Chang, Delay variation tolerance for domino circuits, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Bipul C. Paul , Kaushik Roy, Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits, Journal of Electronic Testing: Theory and Applications, v.22 n.2, p.115-124, April 2006
	N. Ranganathan , U. Gupta , V. Mahalingam, Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Murari Mani , Mahesh Sharma , Michael Orshansky, Application of fast SOCP based statistical sizing in the microprocessor design flow, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	A. K. Singh , M. Mani , M. Orshansky, Statistical technology mapping for parametric yield, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.511-518, November 06-10, 2005, San Jose, CA
	M. R. Guthaus , N. Venkateswarant , C. Visweswariaht , V. Zolotov, Gate sizing using incremental parameterized statistical timing analysis, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.1029-1036, November 06-10, 2005, San Jose, CA
	D. Sinha , N. V. Shenoy , Hai Zhou, Statistical gate sizing for timing yield optimization, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.1037-1041, November 06-10, 2005, San Jose, CA
	Cristinel Ababei , Kia Bazargan, Placement Method Targeting Predictability Robustness and Performance, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.81, November 09-13, 2003
	Aseem Agarwal , David Blaauw , Vladimir Zolotov, Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.900, November 09-13, 2003
	Osama Neiroukh , Xiaoyu Song, Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques, Proceedings of the conference on Design, Automation and Test in Europe, p.294-299, March 07-11, 2005
	Animesh Datta , Swarup Bhunia , Saibal Mukhopadhyay , Nilanjan Banerjee , Kaushik Roy, Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies, Proceedings of the conference on Design, Automation and Test in Europe, p.926-931, March 07-11, 2005
	Aseem Agarwal , Kaviraj Chopra , David Blaauw, Statistical Timing Based Optimization using Gate Sizing, Proceedings of the conference on Design, Automation and Test in Europe, p.400-405, March 07-11, 2005
	Vivek Joshi , David Blaauw , Dennis Sylvester, Soft-edge flip-flops for improved timing yield: design and optimization, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Upavan Gupta , Nagarajan Ranganathan, An expected-utility based approach to variation aware VLSI optimization under scarce information, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Jifeng Chen , Jin Sun , Janet Meilin Wang, Robust interconnect communication capacity algorithm by geometric programming, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA
	Cristiano Forzan , Davide Pandini, Statistical static timing analysis: A survey, Integration, the VLSI Journal, v.42 n.3, p.409-435, June, 2009
	Michael Orshansky , Wei-Shen Wang, Statistical analysis of circuit timing using majorization, Communications of the ACM, v.52 n.8, August 2009