Wave steered FSMs

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Wave steered FSMs

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 270 - 276

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Luca Macchiarulo	University of California, Santa Barbara
Shih-Ming Shu	University of California, Santa Barbara
Malgorzata Marek-Sadowska	University of California, Santa Barbara

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 7, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R Ashar, S. Devadas and A.R.Newton: Optimum and Heuristic Algorithm for an Approach to Finite State Machines Decomposition, IEEE TCAD, March 1991.
	2	L. Benini, E. Macii, M. Poncino, and G. De Micheli: Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs, IEEE TCAD vol. 17 no. 3, March 1998.
	3	V. Bertacco, et al.: Decision Diagrams and Pass Transistor Logic Synthesis, IWLS'97, Lake Tahoe, May 1997.
	4	Premal Buch , Amit Narayan , A. Richard Newton , A. Sangiovanni-Vincentelli, Logic synthesis for large pass transistor circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.663-670, November 09-13, 1997, San Jose, California, United States
	5	C. Chao and H.H. Loomis: High Rate Realization of Finite-State Machines, IEEE Trans. on Comp. vol. C-24, July 1975.
	6	G. De Micheli: Synchronous Logic Synthesis: Algorithms for cycle time minimization, IEEE TCAD, Jan 1991.
	7	S. Devadas and A.R.Newton: Decomposition and Factorization of Sequential Finite State Machines, TCAD, November 1989.
	8	A.D. Friedman: Feedback in Synchronous sequential Switching Circuits, IEEE Trans. on Comp. vol EC-15, June 1966.
	9	Martin Geiger , Thomas Müller-Wipperfürth, FSM decomposition revisited: Algebraic structure theory applied to MCNC benchmark FSMs, Proceedings of the 28th conference on ACM/IEEE design automation, p.182-185, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127661]
	10	Juris Hartmanis, Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics), Prentice-Hall, Inc., Upper Saddle River, NJ, 1966
	11	Andre Hertwig , Hans-Joachim Wunderlich, Fast Controllers for Data Dominated Applications, Proceedings of the 1997 European conference on Design and Test, p.84, March 17-20, 1997
	12	Youpyo Hong , Peter A. Beerel , Jerry R. Burch , Kenneth L. McMillan, Safe BDD minimization using don't cares, Proceedings of the 34th annual conference on Design automation, p.208-213, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266068]
	13	Zvi Kohavi , Richard W. Hamming , Edward A. Feigenbaum, Switching and Finite Automata Theory: Computer Science Series, McGraw-Hill Higher Education, 1990
	14	K. Lam and S. Devadas: Performance-Oriented Decomposition of Sequential Machines, ISCAS '90, New Orleans, May 1990.
	15	B. Lin and A.R. Newton: Synthesis of Multiple Level Logic from Symbolic High-Level Description Languages, IFIP Int.1 Conf. on VLSI, August 1989.
	16	H.-D. Lin, D.G. Messerschmitt: Finite state machine has unlimited concurrency. IEEE Transactions on Circuits and Systems, vol.38, (no.5), May 1991.
	17	Arindam Mukherjee , Ranganathan Sudhakar , Malgorzata Marek-Sadowska , Stephen I. Long, Wave steering in YADDs: a novel non-iterative synthesis and layout technique, Proceedings of the 36th ACM/IEEE conference on Design automation, p.466-471, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309981]
	18	A. Mukherjee, M. Marek-Sadowska, S.I. Long: Wave Pipelining YADDs, CICC'99, San Diego, 1999.
	19	M. Shamanna, K. Cameron, S.R. Whitaker: Multipleinput, Multiple-output Pass Transistor Logic, Int'l J. Electronics vol. 79 n. 1, July 1995.
	20	F. Somenzi: CUDD: CU Decision Diagram Package Release 2.3.0, University of Colorado at Boulder, 1998.
	21	K. Taki: A Survey for Pass-Transistor Logic Technologies, ASP-DAC'98, Yokohama, February 1998.
	22	T. Villa: NOVA: state assignment of finite state machines for optimal two-level implementation, IEEE TCAD, Sept. 1990.

CITED BY 4

	Amit Singh , Arindam Mukherjee , Malgorzata Marek-Sadowska, Interconnect pipelining in a throughput-intensive FPGA architecture, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.153-160, February 2001, Monterey, California, United States
	Amit Singh , Arindam Mukherjee , Malgorzata Marek-Sadowska, Latency and latch count minimization in wave steered circuits, Proceedings of the 38th conference on Design automation, p.383-388, June 2001, Las Vegas, Nevada, United States
	Amit Singh , Arindam Mukherjee , Luca Macchiarulo , Malgorzata Marek-Sadowska, PITIA: an FPGA for throughput-intensive applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.354-363, June 2003
	Luca Macchiarulo , Shih-Min Shu , Malgorzata Marek-Sadowska, Pipelining Sequential Circuits with Wave Steering, IEEE Transactions on Computers, v.53 n.9, p.1205-1210, September 2004