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Automatic lighthouse generation for directed state space search
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Paris, France
Pages: 237 - 242  
Year of Publication: 2000
ISBN:1-58113-244-1
Authors
Praveen Yalagandula  ECE Department, The University of Texas, Austin, TX
Vigyan Singhal  Tempus Fugit, Inc., 525 Curtis St, Albany, CA
Adnan Aziz  ECE Department, The University of Texas, Austin, TX
Sponsors
EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 8,   Citation Count: 4
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132-136, March 1994.
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E Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Transactions on Computers, C-31:215-222, 1981.
 
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Collaborative Colleagues:
Praveen Yalagandula: colleagues
Vigyan Singhal: colleagues
Adnan Aziz: colleagues