A BIST scheme for on-chip ADC and DAC testing

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A BIST scheme for on-chip ADC and DAC testing

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 216 - 220

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Jiun-Lang Huang	Electrical and Computer Engineering, University of California, Santa Barbara
Chee-Kian Ong	Electrical and Computer Engineering, University of California, Santa Barbara
Kwang-Ting Cheng	Electrical and Computer Engineering, University of California, Santa Barbara

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 48, Citation Count: 13

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. F. Toner , Gordon W. Roberts, A BIST Scheme for an SNR Test of a Sigma-Delta ADC, Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them, p.805-814, October 17-21, 1993
	2	Karim Arabi , Bozena Kaminska , Janusz Rzeszut, A new built-in self-test approach for digital-to-analog and analog-to-digital converters, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.491-494, November 06-10, 1994, San Jose, California, United States
	3	K. Arabi , B. Kaminska, Efficient and accurate testing of analog-to-digital converters using oscillation-test method, Proceedings of the 1997 European conference on Design and Test, p.348, March 17-20, 1997
	4	Stephen K. Sunter , Naveena Nagi, A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST, Proceedings of the IEEE International Test Conference, p.389-395, November 03-05, 1997
	5	R. de Vries , T. Zwemstra , E. M. J. G. Bruls , P. P. L. Regtien, Built-in self-test methodology for A/D converters, Proceedings of the 1997 European conference on Design and Test, p.353, March 17-20, 1997
	6	C. L. Wey. Built-in self-test design of current-mode algorithmic analog-to-digital converters. IEEE Transactions on Instrumentation and Measurement, 46(3):667-71, June 1997.
	7	Benoit Dufort , Gordon W. Roberts, Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated Streams, Proceedings of the IEEE International Test Conference, p.396-405, November 03-05, 1997
	8	Matthew Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits, IEEE Computer Society Press, Los Alamitos, CA, 1987

CITED BY 13

	Eduardo J. Peralías , Adoración Rueda , José L. Huertas, New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters, Journal of Electronic Testing: Theory and Applications, v.17 n.5, p.373-383, October 2001
	Ji Hwan (Paul) Chun , Hak-soo Yu , Jacob A. Abraham, An efficient linearity test for on-chip high speed ADC and DAC using loop-back, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Kumar Parthasarathy , Turker Kuyel , Dana Price , Le Jin , Degang Chen , Randall Geiger, BIST and production testing of ADCs using imprecise stimulus, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.4, p.522-545, October 2003
	Sunil Rafeeque K.P. , Vinita Vasudevan, A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs, Journal of Electronic Testing: Theory and Applications, v.20 n.6, p.623-638, December 2004
	Maria Gloria Flores , Marcelo Negreiros , Luigi Carro , Altamiro A. Susin , Felipe R. Clayton , Cristiano Benevento, Low Cost BIST for Static and Dynamic Testing of ADCs, Journal of Electronic Testing: Theory and Applications, v.21 n.3, p.283-290, June 2005
	Chee-Kian Ong , Kwang-Ting (Tim) Cheng , Li-C. Wang, Delta-sigma modulator based mixed-signal BIST architecture for SoC, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Anuja Sehgal , Sule Ozev , Krishnendu Chakrabarty, Test infrastructure design for mixed-signal SOCs with wrapped analog cores, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.3, p.292-304, March 2006
	Doris Lupea , Udo Pursche , Hans-Joachim Jentschel, RF-BIST: Loopback Spectral Signature Analysis, Proceedings of the conference on Design, Automation and Test in Europe, p.10478, March 03-07, 2003
	Hsin-Wen Ting , Cheng-Wu Lin , Bin-Da Liu , Soon-Jyh Chang, Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST, Journal of Electronic Testing: Theory and Applications, v.23 n.6, p.549-558, December 2007
	Shalabh Goyal , Abhijit Chatterjee , Michael Purtell, A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters, Journal of Electronic Testing: Theory and Applications, v.23 n.1, p.95-106, February 2007
	Anuja Sehgal , Fang Liu , Sule Ozev , Krishnendu Chakrabarty, Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores, Proceedings of the conference on Design, Automation and Test in Europe, p.50-55, March 07-11, 2005
	Geng Hu , Hong Wang , Shiyuan Yang, Combined Self-Test of Analog Portion and ADCs in Integrated Mixed-Signal Circuits, IEICE - Transactions on Information and Systems, v.E91-D n.8, p.2134-2140, August 2008
	Hao-Chiao Hong , Sheng-Chuan Liang, A decorrelating design-for-digital-testability scheme for Σ-Δ modulators, IEEE Transactions on Circuits and Systems Part I: Regular Papers, v.56 n.1, p.60-73, January 2009