Constructive library-aware synthesis using symmetries

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Constructive library-aware synthesis using symmetries

Full text

Publisher Site , Pdf

Pdf (205 KB)

Source

Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 208 - 215

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Victor N. Kravets	Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI
Karem A. Sakallah	Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 15, Citation Count: 10

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/343647.343734 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	L. Benini, P. Vuillod, and G. De Micheli. Iterative re-mapping for logic circuits. IEEE TCAD IC, CAD-17(10):948- 964, October 1998.
	2	F.M. Brown. Boolean Reasoning. Kluwer Academic Publishers, Boston, 1990.
	3	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	4	D.L. Dietmeyer and P. Schneider. Identification of symmetry, redundancy and equivalence of boolean functions. IEEE TEC, EC-16(6):804-807, December 1967.
	5	C.R.Edwards andS. L. Hurst. Adigital synthesis procedure under function symmetries and mapping methods. IEEE TC, C-27:985-997, 1978.
	6	B.-G. Kim and D. L. Dietmeyer. Multilevel logic synthesis of symmetric switching functions. IEEE TCAD IC, 10(4):436-446, April 1991.
	7	Wolfgang Kunz , Dominik Stoffel , Vishwani D. Agrawal , Randal E. Bryant, Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques, Kluwer Academic Publishers, Norwell, MA, 1997
	8	Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula, BDD based decomposition of logic functions with application to FPGA synthesis, Proceedings of the 30th international conference on Design automation, p.642-647, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165078]
	9	Eric Lehman , Yosinori Watanabe , Joel Grodstein , Heather Harkness, Logic decomposition during technology mapping, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.264-271, November 05-09, 1995, San Jose, California, United States
	10	Dirk Möller , Janett Mohnke , Michael Weber, Detection of symmetry of Boolean functions represented by ROBDDs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.680-684, November 07-11, 1993, Santa Clara, California, United States
	11	Rajeev Murgai , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Optimum functional decomposition using encoding, Proceedings of the 31st annual conference on Design automation, p.408-414, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196440]
	12	J.P. Roth and R. Karp. Minimization over boolean graphs. IBM J. Res. and Develop., 6(2):227-238, April 1962.
	13	Hiroshi Sawada , Takayuki Suyama , Akira Nagoya, Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.353-358, November 05-09, 1995, San Jose, California, United States
	14	H. Sawada , S. Yamashita , A. Nagoya, Restructuring logic representations with easily detectable simple disjunctive decompositions, Proceedings of the conference on Design, automation and test in Europe, p.755-761, February 23-26, 1998, Le Palais des Congrés de Paris, France
	15	C. Scholl, D. Moiler, P. Molitor, and R. Drechsler. BDD minimization using symmetries. IEEE TCAD IC, 18(2):81- 100, February 1999.
	16	E.M. Sentovich. SIS: A system for sequential circuit synthesis. Technical Report UCB/ERL M92/41, UC Berkeley, May 1992.
	17	F. Somenzi. CUDD: CU Decision Diagram Package. University of Colorado, Boulder, 2.1.2 edition, April 1997.
	18	Bernd Wurth , Klaus Eckl , Kurt Antreich, Functional multiple-output decomposition: theory and an implicit algorithm, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.54-59, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217506]
	19	S. Yang. Logic synthesis and optimization benchmarks user guide- vet. 3.0. MCNC, Res. Triangle Park, NC, Jan. 1991.

CITED BY 10

	Victor N. Kravets , Karem A. Sakallah, Resynthesis of multi-level circuits under tight constraints using symbolic optimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.687-693, November 10-14, 2002, San Jose, California
	Jin S. Zhang , Malgorzata Chrzanowska-Jeske , Alan Mishchenko , Jerry R. Burch, Detecting support-reducing bound sets using two-cofactor symmetries, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Victor N. Kravets , Karem A. Sakallah, Generalized symmetries in boolean functions, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Mariusz Rawski , Henry Selvaraj , Tadeusz Łuba, An application of functional decomposition in ROM-based FSM implementation in FPGA devices, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.6-7, p.424-434, June-July 2005
	Kuo-Hua Wang , Jia-Hung Chen, Symmetry detection for incompletely specified functions, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	L. Jóźwiak , S. Biegański , A. Chojnacki, Information-driven circuit synthesis with the pre-characterized gate libraries, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.6-7, p.405-423, June-July 2005
	Kuo-Hua Wang , Jia-Hung Chen, K-disjointness paradigm with application to symmetry detection for incompletely specified functions, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Fadi A. Aloul , Arathi Ramani , Igor L. Markov , Karem A. Sakallah, Solving difficult SAT instances in the presence of symmetry, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	S. Chatterjee , A. Mishchenko , R. Brayton , X. Wang , T. Kam, Reducing structural bias in technology mapping, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.519-526, November 06-10, 2005, San Jose, CA
	Alan Mishchenko , Robert Brayton , Satrajit Chatterjee, Boolean factoring and decomposition of logic networks, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California