Transformational placement and synthesis

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Transformational placement and synthesis

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 194 - 201

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Wilm Donath	IBM TJ Watson Research Center, Yorktown Heights
Prabhakar Kudva	IBM TJ Watson Research Center, Yorktown Heights
Leon Stok	IBM TJ Watson Research Center, Yorktown Heights
Lakshmi Reddy	IBM Server Group, Hopewell Junction, NY
Andrew Sullivan	IBM Server Group, Hopewell Junction, NY
Kanad Chakraborty	IBM Server Group, Hopewell Junction, NY
Paul Villarrubia	IBM Server Group, Austin, TX

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 8, Citation Count: 21

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. Alpert, T. Chan, A.B.Kahng, I. Markov, and R Mulet. Faster minimization of linear wirelength for global placement. IEEE Transactions on Computer-AidedDesign, 17(1), Jan. 1998.
	2	Charles J. Alpert , Jen-Hsin Huang , Andrew B. Kahng, Multilevel circuit partitioning, Proceedings of the 34th annual conference on Design automation, p.530-533, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266275]
	3	Frederik Beeftink , Prabhakar Kudva , David Kung , Leon Stok, Gate-size selection for standard cell libraries, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.545-550, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289084]
	4	B.Krishnamurthy. An improved min-cut algorithm for partitioning VLSI networks. IEEE Transactions on Computer-Aided Design, pages 438-446, 1984.
	5	Jason Cong , Lei He , Cheng-Kok Koh , Patrick H. Madden, Performance optimization of VLSI interconnect layout, Integration, the VLSI Journal, v.21 n.1-2, p.1-94, Nov. 1996 [doi>10.1016/S0167-9260(96)00008-9]
	6	W. E. Donath. Equivalence of memory to random logic. IBM Journal of Research and Development, pages 401-407, September 1974.
	7	W. E. Donath. Wire length distribution for placements of computer logic. IBM Journal of Research and Development, pages 152-155, May 1981.
	8	Performance Driven Optimization of Network Length in Physical Placement, Proceedings of the 1999 IEEE International Conference on Computer Design, p.258, October 10-13, 1999
	9	Wilm E. Donath , Reini J. Norman , Bhuwan K. Agrawal , Stephen E. Bello , Sang Yong Han , Jerome M. Kurtzberg , Paul Lowy , Roger I. McMillan, Timing driven placement using complete path delays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.84-89, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123232]
	10	D. Hathaway, R. Abato, A. Drumm, and L. van Ginneken. Incremental timing analysis. Technical report, 1996. IBM, U.S. patent 5,508,937.
	11	An integrated placement and synthesis approach for timing closure of PowerPC/sup TM/ microprocessors, Proceedings of the 1997 International Conference on Computer Design (ICCD '97), p.206, October 12-15, 1997
	12	Lalgudi N. Kannan , Peter R. Suaris , Hong-Gee Fang, A methodology and algorithms for post-placement delay optimization, Proceedings of the 31st annual conference on Design automation, p.327-332, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196399]
	13	George Karypis , Rajat Aggarwal , Vipin Kumar , Shashi Shekhar, Multilevel hypergraph partitioning: application in VLSI domain, Proceedings of the 34th annual conference on Design automation, p.526-529, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266273]
	14	K. Kleinhans, G. Sigl, E Johannes, and K.J.Antreich. Gordian: VLSI placement by quadratic programming and slicing optimization. IEEE Transactions on Computer-Aided Design, pages 356-365, 1991.
	15	K. L. Shepard , S. M. Carey , E. K. Cho , B. W. Curran , R. F. Hatch , D. E. Hoffman , S. A. McCabe , G. A. Northrop , R. Seigler, Design methodology for the S/390 parallel enterprise server G4 microprocessors, IBM Journal of Research and Development, v.41 n.4-5, p.515-547, July/Sept. 1997
	16	M. T.-C. Lee and et. al. Incremental timing optimization for physical design by interacting logic restructuring and layout. International Workshop in Logic Synthesis, pages 508-513, 1998.
	17	Jinan Lou , Amir H. Salek , Massoud Pedram, An exact solution to simultaneous technology mapping and linear placement problem, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.671-675, November 09-13, 1997, San Jose, California, United States
	18	Masako Murofushi , Takashi Ishioka , Masami Murakata , Takashi Mitsuhashi, Layout driven re-synthesis for low power consumption LSIs, Proceedings of the 34th annual conference on Design automation, p.666-669, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266314]
	19	Lawrence Pileggi, Timing metrics for physical design of deep submicron technologies, Proceedings of the 1998 international symposium on Physical design, p.28-33, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274539]
	20	Majid Sarrafzadeh , David Knol , Gustavo Tellez, Unification of budgeting and placement, Proceedings of the 34th annual conference on Design automation, p.758-761, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266364]
	21	A. Srinivasan, K. Chaudhary, and E.S.Kuh. RITUAL: A performance driven placement algorithm for small cell ICs. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 48-51, Nov. 1991.
	22	Guenter Stenz , Bernhard M. Riess , Bernhard Rohfleisch , Frank M. Johannes, Timing driven placement in interaction with netlist transformations, Proceedings of the 1997 international symposium on Physical design, p.36-41, April 14-16, 1997, Napa Valley, California, United States [doi>10.1145/267665.267676]
	23	L. Stok , D. S. Kung , D. Brand , A. D. Drumm , L. N. Reddy , N. Hieter , D. J. Geiger , H. H. Chao , P. J. Osler , A. J. Sullivan, BooleDozer: logic synthesis for ASICs, IBM Journal of Research and Development, v.40 n.4, p.407-430, July 1996
	24	Ivan E. Sutherland , Robert F. Sproull, Logical effort: designing for speed on the back of an envelope, Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI, p.1-16, April 1991
	25	W.C.Elmore. The transient response of damped linear networks with particular regard to wideband amplifiers. Journal of Applied Physics, 19(1):55-63, 1948.

CITED BY 21

	Olivier Coudert, Logical and physical design: a flow perspective, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	David E. Lackey , Paul S. Zuchowski , Juergen Koehl, Designing mega-ASICs in nanogate technologies, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Saurabh N. Adya , Mehmet C. Yildiz , Igor L. Markov , Paul G. Villarrubia , Phiroze N. Parakh , Patrick H. Madden, Benchmarking for large-scale placement and beyond, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Victor N. Kravets , Prabhakar Kudva, Understanding metrics in logic synthesis for routability enhancement, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
	Shyam Ramji , Nagu R. Dhanwada, Design topology aware physical metrics for placement analysis, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Yiu-Hing Chan , Prabhakar Kudva , Lisa Lacey , Greg Northrop , Thomas Rosser, Physical synthesis methodology for high performance microprocessors, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Ruchir Puri , Leon Stok , John Cohn , David Kung , David Pan , Dennis Sylvester , Ashish Srivastava , Sarvesh Kulkarni, Pushing ASIC performance in a power envelope, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Charles J. Alpert , Gopal Gandham , Miloš Hrkić , Jiang Hu , Stephen T. Quay, Porosity aware buffered steiner tree construction, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Haoxing Ren , David Z. Pan , David S. Kung, Sensitivity guided net weighting for placement driven synthesis, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Ruchir Puri , David S. Kung , Anthony D. Drumm, Fast and accurate wire delay estimation for physical synthesis of large ASICs, Proceedings of the 12th ACM Great Lakes symposium on VLSI, April 18-19, 2002, New York, New York, USA
	T. R. Bednar , P. H. Buffet , R. J. Darden , S. W. Gould , P. S. Zuchowski, Issues and strategies for the physical design of system-on-a-chip ASICs, IBM Journal of Research and Development, v.46 n.6, p.661-674, November 2002
	Thomas Kutzschebauch , Leon Stok, Congestion aware layout driven logic synthesis, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Ting-Yuan Wang , Jeng-Liang Tsai , Charlie Chung-Ping Chen, Sensitivity guided net weighting for placement driven synthesis, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Renato F. Hentschke , Jagannathan Narasimhan , David Kung, Improving run times by pruned application of synthesis transforms, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
	Robert Lembach , Rafael A. Arce-Nazario , Donald Eisenmenger , Cory Wood, A diagnostic method for detecting and assessing the impact of physical design optimizations on routing, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Charles J. Alpert , Gi-Joon Nam , Paul G. Villarrubia, Free space management for cut-based placement, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.746-751, November 10-14, 2002, San Jose, California
	Michael D. Moffitt , David A. Papa , Zhuo Li , Charles J. Alpert, Path smoothing via discrete optimization, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	S. K. Karandikar , S. S. Sapatnekar, Logical effort based technology mapping, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.419-422, November 07-11, 2004
	Shrirang K. Karandikar , Sachin S. Sapatnekar, Fast Comparisons of Circuit Implementations, Proceedings of the conference on Design, automation and test in Europe, p.20910, February 16-20, 2004
	Kai-hui Chang , Igor L. Markov , Valeria Bertacco, SafeResynth: A new technique for physical synthesis, Integration, the VLSI Journal, v.41 n.4, p.544-556, July, 2008
	Huan Ren , Shantanu Dutt, Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California