Layout compaction for yield optimization via critical area minimization

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Layout compaction for yield optimization via critical area minimization

Full text

Publisher Site , Pdf

Pdf (79 KB)

Source

Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 122 - 127

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Youcef Bourai	Electrical Engineering Department, University of Washington Box 352500, Seattle, Washington
C.-J. Richard Shi	Electrical Engineering Department, University of Washington Box 352500, Seattle, Washington

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 19, Citation Count: 6

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/343647.343717 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	G. A. Allen et al. "A yield improvement technique for IC layout using local design rules, "IEEE Transactions on Computer Aided Design, vol.11, no. 11, pp.1355-1360, Nov. 1992.
	2	Cyrus Bamji , Enrico Malavasi, Enhanced network flow algorithm for yield optimization, Proceedings of the 33rd annual conference on Design automation, p.746-751, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240660]
	3	V. K. R. Chiluvuri and I. Koren, Layout-synthesis techniques for yield enhancement , IEEE Transactions on Semiconductors and manufacturing, vol. 8:2 pp. 178-187, May 1995.
	4	I. Koren and H. C. Stapper, Yield models for defect tolearnt VLSI circuits: A review, in Defect and Fault tolerance on VLSI Systems, vol. 1, I. Koren Ed. New-York: Plenum, pp.1- 21, 1989.
	5	Sching L. Lin , Jonathan Allen, Minplex—a compactor that minimizes the bounding rectangle and individual rectangles in a layout, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.123-130, July 1986, Las Vegas, Nevada, United States
	6	J. K. Ousterhout, Corner stitching: A data-structuring technique for VLSI layout tools, IEEE Transactions on Computer Aided-Design of integrated Circuits and Systems, vol. CAD-3, no.1, pp. 87-100, January 1984.
	7	S. Sastry and A. Parker, The complexity of two dimensional compaction of VLSI layouts, in Proc. Int. Conf. on Circuits and Computers, pp. 402-406, 1982.
	8	Hua Xue , Chennian Di , Jochen A. G. Jess, Fast Multi-Layer Critical Area Computation, Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p.117-124, October 27-29, 1993
	9	Hua Xue , Chennian Di , J. A. G. Jess, A net-oriented method for realistic fault analysis, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.78-83, November 07-11, 1993, Santa Clara, California, United States

CITED BY 6

	José Pineda de Gyvez, Yield modeling and BEOL fundamentals, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.135-163, March 31-April 01, 2001, Sonoma, California, United States
	Tetsuya Iizuka , Makoto Ikeda , Kunihiro Asada, Timing-driven cell layout de-compaction for yield optimization by critical area minimization, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Qiang Zhou , Yi-Ci Cai , Duo Li , Xian-Long Hong, A yield-driven gridless router, Journal of Computer Science and Technology, v.22 n.5, p.653-660, September 2007
	Minsik Cho , Hua Xiang , Ruchir Puri , David Z. Pan, TROY: track router with yield-driven wire planning, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Tetsuya Iizuka , Makoto Ikeda , Kunihiro Asada, Timing-aware cell layout de-compaction for yield optimization by critical area minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.6, p.716-720, June 2007
	David Z. Pan , Minsik Cho, Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea