Layout-oriented synthesis of high performance analog circuits

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Layout-oriented synthesis of high performance analog circuits

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 53 - 57

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Mohamed Dessouky	Université Paris VI (55/65), Laboratoire LIP6-ASIM, 4 Place Jussieu., 75252 Paris Cedex 05, France
Marie-Minerve Louërat	Université Paris VI (55/65), Laboratoire LIP6-ASIM, 4 Place Jussieu., 75252 Paris Cedex 05, France
Jacky Porte	École Nationale Supéerieure, des Télécommunications, 46 Rue Barrault, 75634 Paris Cedex 13, France

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 5, Downloads (12 Months): 24, Citation Count: 8

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J. M. Cohn, R. A. Rutenbar, and L. R. Carley. KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing. IEEE J. of Solid-State Circuits, 26(3):330-342, Mar. 1991.
	2	J. D. Conway and G. G. Schrooten. An Automatic Layout Generator for Analog Circuits. In Proc. European Design Automation Conf., pages 513-519, 1992.
	3	M. G. R. Degrauwe and et. al. IDAC: An Interactive Design Tool for Analog CMOS Circuits. IEEE J. of Solid-State Circuits, 22(6):1106-1115, Dec. 1987.
	4	K. Lampaert, G. Gielen, and W. M. Sansen. A Performance- Driven Placement Tool for Analog Integrated Circuits. IEEE J. of Solid-State Circuits, 30(7):773-780, July 1995.
	5	E. Malavasi, E. Charbon, E. Felt, and A. Sangiovanni- Vincentelli. Automation of ICL Layout with Analog Constraints. IEEE Trans. Computer-Aided Design, 15(8):923- 942, Aug. 1996.
	6	E. Malavasi and D. Pandini. Optimum CMOS Stack Generation with Analog Constraints. IEEE Trans. Computer-Aided Design, 14(1):107-122, Jan. 1995.
	7	E. S. Ochotta, R. A. Rutenbar, and L. R. Carley. Synthesis of high-performace analog circuits in ASTRX/OBLX. IEEE Trans. Computer-Aided Design, 15(3):273-294, Mar. 1996.
	8	H. Onodera, H. Kanbara, and K. Tamaru. Operational- Amplifier Compilation with Performance Optimization. IEEE J. of Solid-State Circuits, 25(2):466-473, Apr. 1990.
	9	B.R. Owen, R. Duncan, S. Jantzi, C. Ouslis, S. Rezania, and K. Martin. BALLISTIC: An Analog Layout Language. In Proc. IEEE Custom Integrated Circuits Conf., 1995.
	10	M. Wolf and U. Kleine. Reliability Driven Module Generation for Analog Layouts. In Proc. Int. Symposium on Circuits and Systems, pages 412-415, June 1999.

CITED BY 9

	Raoul F. Badaoui , Hemanth Sampath , Anuradha Agarwal , Ranga Vemuri, A high level language for pre-layout extraction in parasite-aware analog circuit synthesis, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	M. Dessouky , A. Kaiser , M. Louërat , A. Greiner, Analog design for reuse - case study: very low-voltage sigma-delta modulator, Proceedings of the conference on Design, automation and test in Europe, p.353-360, March 2001, Munich, Germany
	Anuradha Agarwal , Hemanth Sampath , Veena Yelamanchili , Ranga Vemuri, Fast and accurate parasitic capacitance models for layout-aware, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Fabrice Kordon , Luqi, An Introduction to Rapid System Prototyping, IEEE Transactions on Software Engineering, v.28 n.9, p.817-821, September 2002
	I-Lun Tseng , Adam Postula, Partitioning parameterized 45-degree polygons with constraint programming, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.3, p.1-29, July 2008
	Almitra Pradhan , Ranga Vemuri, A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Mukesh Ranjan , Wim Verhaegen , Anuradha Agarwal , Hemanth Sampath , Ranga Vemuri , Geoges Gielen, Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models, Proceedings of the conference on Design, automation and test in Europe, p.10604, February 16-20, 2004
	Anuradha Agarwal , Hemanth Sampath , Veena Yelamanchili , Ranga Vemuri, Accurate Estimation of Parasitic Capacitances in Analog Circuits, Proceedings of the conference on Design, automation and test in Europe, p.21364, February 16-20, 2004
	Ender Yilmaz , Günhan Dündar, Analog layout generator for CMOS circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.1, p.32-45, January 2009