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Efficient power co-estimation techniques for system-on-chip design
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Paris, France
Pages: 27 - 34  
Year of Publication: 2000
ISBN:1-58113-244-1
Authors
Marcello Lajolo  Politecnico di Torino
Anand Raghunathan  NEC, C&C Research Labs, Princeton, NJ
Sujit Dey  UC San Diego, La Jolla, CA
Sponsors
EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 15,   Citation Count: 14
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J. Rabaey and M. Pedram (Editors), Low Power Design Methodologies. Kluwer Academic Publishers, Norwell, MA, 1996.
 
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T. Sato, Y. Ootaguro, M. Nagamatsu, and H. Tago, "Evaluation of architecture-level power estimation for CMOS RISC processors," in Proc. Symp. Low Power Electronics, pp. 44-45, Oct. 1995.
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J. Buck, S. Ha, E. Lee, and D. Masserchmitt, "Ptolemy: A framework for simulating and prototyping heterogeneous systems," International Journal on Computer Simulation Special Issue on Simulation Software Management, Jan. 1994.
 
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M. Lajolo, L. Lavagno, and A. Sangiovanni-Vincentelli, "Fast instruction cache simulation strategies in a hardware/software co-design environment," in Proc. Asia and South Pacific Design Automation Conf., Jan. 1999.
 
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CITED BY  14

Collaborative Colleagues:
Marcello Lajolo: colleagues
Anand Raghunathan: colleagues
Sujit Dey: colleagues