Analysis of high-level address code transformations for programmable processors

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Analysis of high-level address code transformations for programmable processors

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 9 - 13

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Sumit Gupta	Department of Information and Computer Science, Univ. of California at Irvine
Miguel Miranda
Francky Catthoor
Rajesh Gupta

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

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ACM New York, NY, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 12

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	Miguel Miranda , Francky Catthoor , Martin Janssen , Hugo de Man, ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures, Proceedings of the 9th international symposium on System synthesis, p.20, November 06-08, 1996
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	13	Miguel A. Miranda , Francky V. M. Catthoor , Martin Janssen , Hugo J. De Man, High-level address optimization and synthesis techniques for data-transfer-intensive applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.677-686, Dec. 1998 [doi>10.1109/92.736141]
	14	Stefaan Note , Werner Geurts , Francky Catthoor , Hugo De Man, Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications, Proceedings of the 28th conference on ACM/IEEE design automation, p.597-602, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127739]
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CITED BY 12

	M. Miranda , C. Ghez , C. Kulkarni , F. Catthoor , D. Verkest, Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	P. R. Panda , F. Catthoor , N. D. Dutt , K. Danckaert , E. Brockmeyer , C. Kulkarni , A. Vandercappelle , P. G. Kjeldsberg, Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.149-206, April 2001
	Rainer Leupers, Code generation for embedded processors, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Sumit Gupta , Mehrdad Reshadi , Nick Savoiu , Nikil Dutt , Rajesh Gupta , Alex Nicolau, Dynamic common sub-expression elimination during scheduling in high-level synthesis, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	Björn Franke , Michael O'boyle, Array recovery and high-level transformations for DSP applications, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.2, p.132-162, May 2003
	C. Kulkarni , C. Ghez , M. Miranda , F. Catthoor , H. De Man, Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications, IEEE Transactions on Computers, v.54 n.1, p.76-81, January 2005
	Sumit Gupta , Rajesh Kumar Gupta , Nikil D. Dutt , Alexandru Nicolau, Coordinated parallelizing compiler optimizations and high-level synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.4, p.441-470, October 2004
	Heiko Falk , Peter Marwedel, Control Flow Driven Splitting of Loop Nests at the Source Code Level, Proceedings of the conference on Design, Automation and Test in Europe, p.10410, March 03-07, 2003
	M. Palkovic , M. Miranda , K. Denolf , P. Vos , F. Catthoor, Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.547, January 07-11, 2002
	J. Ramanujam , Satish Krishnamurthy , Jinpyo Hong , Mahmut Kandemir, Address Code and Arithmetic Optimizations for Embedded Systems, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.619, January 07-11, 2002
	Guillermo Talavera , Murali Jayapala , Jordi Carrabina , Francky Catthoor, Address Generation Optimization for Embedded High-Performance Processors: A Survey, Journal of Signal Processing Systems, v.53 n.3, p.271-284, December 2008
	Ittetsu Taniguchi , Murali Jayapala , Praveen Raghavan , Francky Catthoor , Keishi Sakanushi , Yoshinori Takeuchi , Masaharu Imai, Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan