| Unifying behavioral synthesis and physical design |
| Full text |
Pdf
(398 KB)
|
| Source
|
Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 37th Annual Design Automation Conference
table of contents
Los Angeles, California, United States
Pages: 756 - 761
Year of Publication: 2000
ISBN:1-58113-187-9
|
|
Authors
|
|
William E. Dougherty
|
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
|
|
Donald E. Thomas
|
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 3, Downloads (12 Months): 23, Citation Count: 10
|
|
|
ABSTRACT
Our methodology unifies behavioral synthesis and physical design, allowing scheduling, allocation, binding, and placement to occur simultaneously. This is accomplished via set of defined transformation from both domains acting as forces in a single behavioral/physical system. Experiments show results with 50% less area and 10% lower critical path delay than the best results from a commercial behavioral synthesis tool. Our behavioral level area, delay, and individual component location estimates closely match results produced by physical design tools given only pin locations as a starting point.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
|
 |
2
|
Richard J. Cloutier , Donald E. Thomas, The combination of scheduling, allocation, and mapping in a single algorithm, Proceedings of the 27th ACM/IEEE conference on Design automation, p.71-76, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123230]
|
| |
3
|
Design Compiler Reference Manual, Synopsys Inc, 1998.
|
| |
4
|
Devadas, S. and Newton, R., "Algorithms for Hardware Allocation in Data Path Synthesis," IEEE Transactions on Computer-Aided Design, vol. 8, no. 7, July 1989.
|
 |
5
|
|
| |
6
|
|
| |
7
|
Knapp, D., "Fasolt: A Program for Feedback-Driven Data- Path Optimization," IEEE Trans. on CAD, vol. 11, no. 6, July 1992.
|
| |
8
|
Kollig, P., A1-Hashimi, B., "Simultaneous Scheduling, Allocation and Binding in High Level Synthesis," Electronics Letters, vol.33, no.18, 28 Aug. 1997.
|
| |
9
|
|
| |
10
|
McFarland, M. and Kowalski "Incorporating Bottom- Up Design Techniques into Hardware Synthesis," IEEE Trans. on CAD, vol. 9 no. 9, Sep 1990.
|
| |
11
|
Natesan, V., et al., "A Constructive Method for Data Path Area Estimation During High-Level Synthesis," ASP-DAC, 1997.
|
| |
12
|
Silicon Ensemble (DSM) Reference Manual 5.0, Cadence Design Systems, Inc, 1997.
|
 |
13
|
|
 |
14
|
Shantanu Tarafdar , Miriam Leeser , Zixin Yin, Integrating floorplanning in data-transfer based high-level synthesis, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.412-417, November 08-12, 1998, San Jose, California, United States
[doi> 10.1145/288548.289063]
|
| |
15
|
Donald E. Thomas , Elizabeth D. Lagnese , John A. Nestor , Jayanth V. Rajan , Robert L. Blackburn , Robert A. Walker, Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench, Kluwer Academic Publishers, Norwell, MA, 1989
|
| |
16
|
|
| |
17
|
|
| |
18
|
www.ece.cmu.edu/~wed/dac200files.html
|
| |
19
|
|
CITED BY 10
|
|
M. Graziano , G. Masera , G. Piccinini , M. Zamboni, Hierarchical power supply noise evaluation for early power grid design prediction, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.183-188, March 31-April 01, 2001, Sonoma, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
Zhenyu (Peter) Gu , Jia Wang , Robert P. Dick , Hai Zhou, Incremental exploration of the combined physical and behavioral design space, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
|
|
|
|
|
|
|
|
|
Ryan Kastner , Wenrui Gong , Xin Hao , Forrest Brewer , Adam Kaplan , Philip Brisk , Majid Sarrafzadeh, Layout driven data communication optimization for high level synthesis, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
|
|
|
|
|
|
|
|