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Unifying behavioral synthesis and physical design
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents
Los Angeles, California, United States
Pages: 756 - 761  
Year of Publication: 2000
ISBN:1-58113-187-9
Authors
William E. Dougherty  Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas  Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 23,   Citation Count: 10
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ABSTRACT

Our methodology unifies behavioral synthesis and physical design, allowing scheduling, allocation, binding, and placement to occur simultaneously. This is accomplished via set of defined transformation from both domains acting as forces in a single behavioral/physical system. Experiments show results with 50% less area and 10% lower critical path delay than the best results from a commercial behavioral synthesis tool. Our behavioral level area, delay, and individual component location estimates closely match results produced by physical design tools given only pin locations as a starting point.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Design Compiler Reference Manual, Synopsys Inc, 1998.
 
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Devadas, S. and Newton, R., "Algorithms for Hardware Allocation in Data Path Synthesis," IEEE Transactions on Computer-Aided Design, vol. 8, no. 7, July 1989.
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Knapp, D., "Fasolt: A Program for Feedback-Driven Data- Path Optimization," IEEE Trans. on CAD, vol. 11, no. 6, July 1992.
 
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Kollig, P., A1-Hashimi, B., "Simultaneous Scheduling, Allocation and Binding in High Level Synthesis," Electronics Letters, vol.33, no.18, 28 Aug. 1997.
 
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McFarland, M. and Kowalski "Incorporating Bottom- Up Design Techniques into Hardware Synthesis," IEEE Trans. on CAD, vol. 9 no. 9, Sep 1990.
 
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Natesan, V., et al., "A Constructive Method for Data Path Area Estimation During High-Level Synthesis," ASP-DAC, 1997.
 
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Silicon Ensemble (DSM) Reference Manual 5.0, Cadence Design Systems, Inc, 1997.
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www.ece.cmu.edu/~wed/dac200files.html
 
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CITED BY  10

Collaborative Colleagues:
William E. Dougherty: colleagues
Donald E. Thomas: colleagues