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ABSTRACT

Multiprocessing (MP) design verification has been one of the bottlenecks for high performance microprocessor design projects. The problem is getting worse as the design complexity increases and more cache structures are integrated into one single chip. The challenges that MP verification faces today include: huge chip/system simulation model sizes, long simulation cycles, relative inefficiency of the simulation tools compared to uniprocessor, and so on. To solve these challenging problems, we developed a new methodology and simulation flow for an upcoming design in Motorola's G4 generation of microprocessors, MPC74XX1. The key strategy of this methodology was to start MP verification as early as the design implementation started. The same methodology/tool set were first developed for MP verification at the unit level, then reused at the multiple-unit level, and eventually reused at the chip/system level. In this paper, we will present the details of this methodology, and demonstrate why it is effective and efficient in detecting the majority of the MP functional defects at an early stage of the design phase.

REFERENCES

• 1: "The PowerPC Architecture: A Specification for a New Family of RISC Processors", edited by C. May, E. Silha, R. Simpson, and H. Warren, Morgan Kaufmann Publishers, 2nd Edition, 1994.
• 2: "PowerPC User Instruction Set Architecture Book I, Book II, and Book III".
• 3: B. O'Krafka, S. Mandyam, J. Kreulen, R. Raghavan, A. Saha, and N. Malik, "MPTG: A Portable Test Generator for Cache- Coherent Multiprocessors", International Conference on Computers and Communications, 1995, pp 38--44.
• 4: L. Giordano, D. Fields, J. Jalal, and N. Steinke, "Unique MP Verification Techniques for Symmetric Multiprocessing Systems", On-Chip System Design Conference (DesignCon99), pp245--267.
• 5: J. Monaco and J. Kasha, An Automatic Simulation Environment for PowerPC Design Verification", On-Chip System Design Conference (DesignCon95), pp12-1--12-13.
• 6: Jen-Tien Yen , Marie Sullivan , Carlos Montemayor , Pete Wilson , Richard Evers, Overview of PowerPCTM 620 Multiprocessor Verification Strategy, Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test, p.167-174, October 21-25, 1995
• 7: Naras Iyengar, "Motorola's Next PowerPC Microarchitecture with AltiVec Technology", Microprocessor Forum, 1999.

INDEX TERMS

Primary Classification:
  J. Computer Applications

Additional Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION

General Terms:
Design, Measurement, Performance, Theory, Verification