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ABSTRACT
Technology extrapolation — the calibration and prediction of achievable design in future technology generations — drives the evolution of VLSI system architectures, design methodologies, and design tools. This paper describes initial experiences with development and use of GTX, the MARCO GSRC Technology Extrapolation system. GTX provides a robust, portable framework for interactive specification and comparison of modeling choices, e.g., for predicting system cycle time, die size and power dissipation. We use GTX to reveal surprising levels of uncertainty (modeling and parameter sensitivity) in widely-cited cycle-time models that drive recent roadmaps. We also describe new SOI and bulk device models that have been developed for GTX, as well as studies of power dissipation and delay uncertainty under various implementation assumptions for global interconnects.
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CITED BY 16
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Prashant Saxena , Noel Menezes , Pasquale Cocchini , Desmond A. Kirkpatrick, The scaling challenge: can correct-by-construction design help?, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
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Feodor F. Dragan , Andrew B. Kahng , Ion Măndoiu , Sudhakar Muddu , Alexander Zelikovsky, Provably good global buffering using an available buffer block plan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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Yu Cao , Chenming Hu , Xuejue Huang , Andrew B. Kahng , Igor L. Markov , Michael Oliver , Dirk Stroobandt , Dennis Sylvester, Improved a priori terconnect predictions and technology extrapolation in the GTX system, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.3-14, February 2003
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Vishak Venkatraman , Andrew Laffely , Jinwook Jang , Hempraveen Kukkamalla , Zhi Zhu , Wayne Burleson, NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods, Proceedings of the 2004 international workshop on System level interconnect prediction, February 14-15, 2004, Paris, France
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Yu Cao , Chenming Hu , Xuejue Huang , Andrew B. Kahng , Sudhakar Muddu , Dirk Stroobandt , Dennis Sylvester, Effects of global interconnect optimizations on performance estimation of deep submicron design, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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