Convex delay models for transistor sizing

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Convex delay models for transistor sizing

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents

Los Angeles, California, United States

Pages: 655 - 660

Year of Publication: 2000

ISBN:1-58113-187-9

Authors

Mahesh Ketkar	Department of ECE, University of Minnesota, Minneapolis, MN
Kishore Kasamsetty	Department of ECE, University of Minnesota, Minneapolis, MN
Sachin Sapatnekar	Department of ECE, University of Minnesota, Minneapolis, MN

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 25, Citation Count: 6

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ABSTRACT

This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. The delay model is incorporated into a transistor sizing algorithm based on TILOS. The models were characterized by using a set of grid points and then validated using a disjoint data set. The models were found to be within about 10% of SPICE for nearly all of the gate types considered. Also presented are the experimental results of sizing various test circuits.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 6

	Mahesh Ketkar , Sachin S. Sapatnekar, Standby power optimization via transistor sizing and dual threshold voltage assignment, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.375-378, November 10-14, 2002, San Jose, California
	Hsu-Wei Huang , Cheng-Yeh Wang , Jing-Yang Jou, Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.280-283, January 27-30, 2004, Yokohama, Japan
	Zhaojun Wo , Israel Koren, Effective analytical delay model for transistor sizing, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	S. Shah , A. Srivastava , D. Sharma , D. Sylvester , D. Blaauw , V. Zolotov, Discrete Vt assignment and gate sizing using a self-snapping continuous formulation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.705-712, November 06-10, 2005, San Jose, CA
	Frank Huebbers , Ali Dasdan , Yehea Ismail, Multi-layer interconnect performance corners for variation-aware timing analysis, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Seyed-Abdollah Aftabjahani , Linda Milor, Timing analysis with compact variation-aware standard cell models, Integration, the VLSI Journal, v.42 n.3, p.312-320, June, 2009