The role of custom design in ASIC Chips

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The role of custom design in ASIC Chips

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents

Los Angeles, California, United States

Pages: 643 - 647

Year of Publication: 2000

ISBN:1-58113-187-9

Authors

Willaim J. Dally	Computer Systems Laboratory, Stanford University, Stanford, CA
Andrew Chang	Computer Systems Laboratory, Stanford University, Stanford, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 29, Citation Count: 14

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Through floorplanning and tiling data paths, the designer places the critical wires first, before the logic is placed. Crafted datapath cells structure wiring at the other end of the spectrum by keeping local wires short enabling the use of minimum sized drivers. Routing the wires first gives early visibility of timing issues, allows the design to be optimized to drive the exact wire load, and enables the use of fast circuit styles.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	CHANG, ANDREW, VLSI Datapath Choices: Cell-Based Versus Full- Custom, SM Thesis, Massachusetts Institute of Technology, February 1998.
	2	William J. Dally , John W. Poulton, Digital systems engineering, Cambridge University Press, New York, NY, 1998
	3	GRONOWSKI, PAUL E., BOWHILL, WILLIAM J., PRESTON, RONALD P., GOWAN, MICHAEL K., AND ALLMON, RANDY L., High-Perfomance Microprocessor Design, IEEE Journal of Solid-state Circuits. Vo133. No 5., May 1998, pp. 676-686.
	4	David L. Harris , Stuart F. Oberman , Mark A. Horowitz, SRT Division Architectures and Implementations, Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97), p.18, March 06-09, 1997
	5	IBM CORPORATION, SA-27EASICDatabook, February 2000.
	6	KECKLER, STEPHEN W., DALLY, WILLIAM J., CHANG, ANDREW., CARTER, NICHOLAS P., LEE, WHAY SING., "The MIT MuIti-ALU Processor", Hot Chips IX, August 1997, pp 1-8.

CITED BY 14

	Dennis Sylvester , Himanshu Kaul, Future performance challenges in nanometer design, Proceedings of the 38th conference on Design automation, p.3-8, June 2001, Las Vegas, Nevada, United States
	Satoshi Ono , Patrick H. Madden, On structure and suboptimality in placement, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Saurabh N. Adya , Mehmet C. Yildiz , Igor L. Markov , Paul G. Villarrubia , Phiroze N. Parakh , Patrick H. Madden, Benchmarking for large-scale placement and beyond, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Andrew Chang , William J. Dally, Explaining the gap between ASIC and custom power: a custom perspective, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Ian Kuon , Aaron Egier , Jonathan Rose, Design, layout and verification of an FPGA using automated tools, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Victor Zyuban , Sameh W. Asaad , Thomas W. Fox , Anne-Marie Haen , Daniel Littrell , Jaime H. Moreno, Design methodology for semi custom processor cores, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	David A. Papa , Saurabh N. Adya , Igor L. Markov, Constructive benchmarking for placement, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Mihai Budiu , Girish Venkataramani , Tiberiu Chelcea , Seth Copen Goldstein, Spatial computation, ACM SIGARCH Computer Architecture News, v.32 n.5, December 2004
	S. N. Adya , I. L. Markov, Combinatorial techniques for mixed-size placement, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.58-90, January 2005
	Henrik Eriksson , Per Larsson-Edefors , Tomas Henriksson , Christer Svensson, Full-custom vs. standard-cell design flow: an adder case study, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Ian Kuon , Jonathan Rose, Measuring the gap between FPGAs and ASICs, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Mike Hutton , Richard Yuan , Jay Schleicher , Gregg Baeckler , Sammy Cheung , Kar Keng Chua , Hee Kong Phoo, A methodology for FPGA to structured-ASIC synthesis and verification, Proceedings of the conference on Design, automation and test in Europe: Designers' forum, March 06-10, 2006, Munich, Germany
	Lesley Shannon , Paul Chow, SIMPPL: an adaptable SoC framework using a programmable controller IP interface to facilitate design reuse, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.4, p.377-390, April 2007
	Saurabh N. Adya , Igor L. Markov , Paul G. Villarrubia, On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.311, November 09-13, 2003