| Fingerprinting intellectual property using constraint-addition |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 37th Annual Design Automation Conference
table of contents
Los Angeles, California, United States
Pages: 587 - 592
Year of Publication: 2000
ISBN:1-58113-187-9
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Authors
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Gang Qu
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Computer Science Department, University of California, Los Angeles, CA
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Miodrag Potkonjak
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Computer Science Department, University of California, Los Angeles, CA
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Downloads (6 Weeks): 7, Downloads (12 Months): 44, Citation Count: 2
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ABSTRACT
Recently, intellectual property protection (IPP) techniques attracted a great deal of attention from semiconductor, system integration and software companies. A number of watermarking-based techniques have been proposed for IPP. One of the key limitations of watermarking is that it does not facilitate tracing of illegally resold intellectual property (IP). Fingerprinting resolves this problem by providing each customer with a unique instance of functionally identical IP. We propose a general technique which enables fingerprinting at all level of design process and is applicable to an arbitrary optimization step. In particular, we address the following fingerprinting problem: How to generate a large number of high quality solution for a given optimization problem by solving the initial problem only once. In addition we also discuss how to select a subset of k solutions from the pool of n solutions so that the solutions are maximally different.
In order to make our discussion concrete we focus on a single NP-complete problem -- graph coloring. We test the new fingerprinting on a number of standard benchmarks. Interestingly, while on random graphs it is relatively difficult to produce a large number of solutions without nontrivial quality degradation, on all real-life compilation graphs we are able to generate millions of solution which are all optimal.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 2
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Adarsh K. Jain , Lin Yuan , Pushkin R. Pari , Gang Qu, Zero overhead watermarking technique for FPGA designs, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
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