Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips

ABSTRACT

In this chapter, we present a general methodology for the design of custom system-on-chip communication architectures. Our technique is based on the addition of a layer of circuitry, called the Communication Architecture Tuner (CAT), around any existing communication architecture topology. The added layer enhances the ability of the system to adapt to changing communication needs of its constituent components. For example, more critical data may be handled differently, leading to lower communication latencies. The CAT monitors the internal state and communication transactions of each component, and “predicts” the relative importance of each communication transaction in terms of its potential impact on different system-level performance metrics. It then configures the protocol parameters of the underlying communication architecture (e.g., priorities, DMA modes,etc.) to best suit the system's changing communication needs. We illustrate issues and tradeoffs involved in the design of CAT-based communication architectures, and present algorithms to automate the key steps. Experimental results indicate that performance metrics (e.g. number of missed deadlines, average processing time) for systems with CAT-based communication architectures are significantly (sometimes, over an order of magnitude) better than those with conventional communication architectures.

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INDEX TERMS

Primary Classification:
  J. Computer Applications

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS

General Terms:
Algorithms, Design, Measurement, Performance, Standardization, Theory