| Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 37th Annual Design Automation Conference
table of contents
Los Angeles, California, United States
Pages: 513 - 518
Year of Publication: 2000
ISBN:1-58113-187-9
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Authors
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Kanishka Lahiri
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Dept. of Electrical and Computer Engg., University of California, San Diego, CA
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Anand Raghunathan
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C & C Research Labs, NEC USA, Princeton, NJ
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Ganesh Lakshminarayana
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C & C Research Labs, NEC USA, Princeton, NJ
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Sujit Dey
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Dept. of Electrical and Computer Engg., University of California, San Diego, CA
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Downloads (6 Weeks): 3, Downloads (12 Months): 20, Citation Count: 20
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ABSTRACT
In this chapter, we present a general methodology for the design of custom system-on-chip communication architectures. Our technique is based on the addition of a layer of circuitry, called the Communication Architecture Tuner (CAT), around any existing communication architecture topology. The added layer enhances the ability of the system to adapt to changing communication needs of its constituent components. For example, more critical data may be handled differently, leading to lower communication latencies. The CAT monitors the internal state and communication transactions of each component, and “predicts” the relative importance of each communication transaction in terms of its potential impact on different system-level performance metrics. It then configures the protocol parameters of the underlying communication architecture (e.g., priorities, DMA modes,etc.) to best suit the system's changing communication needs.
We illustrate issues and tradeoffs involved in the design of CAT-based communication architectures, and present algorithms to automate the key steps. Experimental results indicate that performance metrics (e.g. number of missed deadlines, average processing time) for systems with CAT-based communication architectures are significantly (sometimes, over an order of magnitude) better than those with conventional communication architectures.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 20
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Sungjoo Yoo , Gabriela Nicolescu , Damien Lyonnard , Amer Baghdadi , Ahmed A. Jerraya, A generic wrapper architecture for multi-processor SoC cosimulation and design, Proceedings of the ninth international symposium on Hardware/software codesign, p.195-200, April 2001, Copenhagen, Denmark
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Sungjoo Yoo , Kyoungseok Rha , Youngchul Cho , Jinyong Jung , Kiyoung Choi, Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model, Proceedings of the eighth international workshop on Hardware/software codesign, p.77-81, May 2000, San Diego, California, United States
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Damien Lyonnard , Sungjoo Yoo , Amer Baghdadi , Ahmed A. Jerraya, Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip, Proceedings of the 38th conference on Design automation, p.518-523, June 2001, Las Vegas, Nevada, United States
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Faraydon Karim , Anh Nguyen , Sujit Dey , Ramesh Rao, On-chip communication architecture for OC-768 network processors, Proceedings of the 38th conference on Design automation, p.678-683, June 2001, Las Vegas, Nevada, United States
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Shankar Mahadevan , Federico Angiolini , Michael Storgaard , Rasmus Grondahl Olsen , Jens Sparso , Jan Madsen, A Network Traffic Generator Model for Fast Network-on-Chip Simulation, Proceedings of the conference on Design, Automation and Test in Europe, p.780-785, March 07-11, 2005
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Franco Fummi , Mirko Loghi , Stefano Martini , Marco Monguzzi , Giovanni Perbellini , Massimo Poncino, Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation, Proceedings of the conference on Design, Automation and Test in Europe, p.798-803, March 07-11, 2005
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