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Hardware-software co-design of embedded reconfigurable architectures
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents
Los Angeles, California, United States
Pages: 507 - 512  
Year of Publication: 2000
ISBN:1-58113-187-9
Authors
Yanbing Li  Synopsys Inc., 700 East Middlefield Rd. Mountain View, CA
Tim Callahan  Department of EECS, Univ. of California, Berkeley, CA
Ervan Darnell  Silicon Spice, 415 East Middlefield Rd., Mountain View, CA
Randolph Harr  Synopsys Inc., 700 East Middlefield Rd. Mountain View, CA
Uday Kurkure  Synopsys Inc., 700 East Middlefield Rd. Mountain View, CA
Jon Stockwood  Synopsys Inc., 700 East Middlefield Rd. Mountain View, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 39,   Downloads (12 Months): 164,   Citation Count: 49
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ABSTRACT

In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically reconfigurable datapath (e.g. an FPGA), and a memory hierarchy. We have developed a framework called Nimble that automatically compiles system-level applications specified in C to executables on the target platform. A key component of this framework is a hardware/software partitioning algorithm that performs fine-grained partitioning (at loop and basic-block levels) of an application to execute on the combined CPU and datapath. The partitioning algorithm optimizes the global application execution time, including the software and hardware execution times, communication time and datapath reconfiguration time. Experimental results on real applications show that our algorithm is effective in rapidly finding close to optimal solutions.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Y. Li and W. Wolf, "Hardware/software co-synthesis with memory hierarchies," IEEE Transactions on CAD, vol. 18, no.10, pp.1405-1417, Oct. 1999.
 
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S. Prakash and A. Parker, "SOS: synthesis of applicationspecific heterogeneous multiprocessor systems," Journal of Parallel and Distributed Computing, vol.16, pp.338-351, 1992.
 
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W. Wolf. "Hardware/software co-design of embedded systems," Proceedings of the IEEE, July 1994.
 
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TSI Telsys, "ACE2 Card Manual", 1998.

CITED BY  49

Collaborative Colleagues:
Yanbing Li: colleagues
Tim Callahan: colleagues
Ervan Darnell: colleagues
Randolph Harr: colleagues
Uday Kurkure: colleagues
Jon Stockwood: colleagues