| Hardware-software co-design of embedded reconfigurable architectures |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 37th Annual Design Automation Conference
table of contents
Los Angeles, California, United States
Pages: 507 - 512
Year of Publication: 2000
ISBN:1-58113-187-9
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Authors
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Yanbing Li
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Synopsys Inc., 700 East Middlefield Rd. Mountain View, CA
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Tim Callahan
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Department of EECS, Univ. of California, Berkeley, CA
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Ervan Darnell
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Silicon Spice, 415 East Middlefield Rd., Mountain View, CA
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Randolph Harr
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Synopsys Inc., 700 East Middlefield Rd. Mountain View, CA
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Uday Kurkure
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Synopsys Inc., 700 East Middlefield Rd. Mountain View, CA
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Jon Stockwood
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Synopsys Inc., 700 East Middlefield Rd. Mountain View, CA
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Downloads (6 Weeks): 39, Downloads (12 Months): 164, Citation Count: 49
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ABSTRACT
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically reconfigurable datapath (e.g. an FPGA), and a memory hierarchy. We have developed a framework called Nimble that automatically compiles system-level applications specified in C to executables on the target platform. A key component of this framework is a hardware/software partitioning algorithm that performs fine-grained partitioning (at loop and basic-block levels) of an application to execute on the combined CPU and datapath. The partitioning algorithm optimizes the global application execution time, including the software and hardware execution times, communication time and datapath reconfiguration time. Experimental results on real applications show that our algorithm is effective in rapidly finding close to optimal solutions.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[doi> 10.1145/309847.310010]
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CITED BY 49
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Clark N. Taylor , Debashis Panigrahi , Sujit Dey, Design of an adaptive architecture for energy efficient wireless image communication, Embedded processor design challenges: systems, architectures, modeling, and simulation-SAMOS, Springer-Verlag New York, Inc., New York, NY, 2002
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Massimo Baleani , Frank Gennari , Yunjian Jiang , Yatish Patel , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
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Paul Pop , Petru Eles , Traian Pop , Zebo Peng, An approach to incremental design of distributed embedded systems, Proceedings of the 38th conference on Design automation, p.450-455, June 2001, Las Vegas, Nevada, United States
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Alberto La Rosa , Luciano Lavagno , Claudio Passerone, A software development tool chain for a reconfigurable processor, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
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Ian Robertson , James Irvine , Patrick Lysaght , David Robinson, Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
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Girish Venkataramani , Walid Najjar , Fadi Kurdahi , Nader Bagherzadeh , Wim Bohm , Jeff Hammes, Automatic compilation to a coarse-grained reconfigurable system-opn-chip, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.4, p.560-589, November 2003
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W. Böhm , J. Hammes , B. Draper , M. Chawathe , C. Ross , R. Rinker , W. Najjar, Mapping a Single Assignment Programming Language to Reconfigurable Systems, The Journal of Supercomputing, v.21 n.2, p.117-130, February 2002
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Walid A. Najjar , Wim Böhm , Bruce A. Draper , Jeff Hammes , Robert Rinker , J. Ross Beveridge , Monica Chawathe , Charles Ross, High-Level Language Abstraction for Reconfigurable Computing, Computer, v.36 n.8, p.63-69, August 2003
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Marco D. Santambrogio , Seda Ogrenci Memik , Vincenzo Rana , Umut A. Acar , Donatella Sciuto, A novel SoC design methodology combining adaptive software and reconfigurable hardware, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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M. Borgatti , A. Capello , U. Rossi , J.-L. Lambert , I. Moussa , F. Fummi , G. Pravadelli, An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems, Proceedings of the conference on Design, Automation and Test in Europe, p.266-271, March 07-11, 2005
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Todor Stefanov , Claudiu Zissulescu , Alexandru Turjan , Bart Kienhuis , Ed Deprettere, System Design Using Kahn Process Networks: The Compaan/Laura Approach, Proceedings of the conference on Design, automation and test in Europe, p.10340, February 16-20, 2004
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Huynh Phung Huynh , Joon Edward Sim , Tulika Mitra, An efficient framework for dynamic reconfiguration of instruction-set customization, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
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Andrew Putnam , Susan Eggers , Dave Bennett , Eric Dellinger , Jeff Mason , Henry Styles , Prasanna Sundararajan , Ralph Wittig, Performance and power of cache-based reconfigurable computing, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009
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