Can recursive bisection alone produce routable placements?

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Can recursive bisection alone produce routable placements?

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents

Los Angeles, California, United States

Pages: 477 - 482

Year of Publication: 2000

ISBN:1-58113-187-9

Authors

Andrew E. Caldwell	UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng	UCLA Computer Science Dept., Los Angeles, CA
Igor L. Markov	UCLA Computer Science Dept., Los Angeles, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 38, Citation Count: 124

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ABSTRACT

This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the state-of-the-art after two decades of research in recursive bisection placement and implement a new placer, called Capo, to empirically study the achievable limits of the approach. From among recently proposed improvements to recursive bisection, Capo incorporates a leading-edge multilevel min-cut partitioner [7], techniques for partitioning with small tolerance [8], optimal min-cut partitioners and end-case min-wirelength placers [5], previously unpublished partitioning tolerance computations, and block splitting heuristics. On the other hand, our “good enough” implementation does not use “overlapping” [17], multi-way partitioners [17, 20], analytical placement, or congestion estimation [24, 35]. In order to run on recent industrial placement instances, Capo must take into account fixed macros, power stripes and rows with different allowed cell orientations. Capo reads industry-standard LEF/DEF, as well as formats of the GSRC bookshelf for VLSI CAD algorithms [6], to enable comparisons on available placement instances in the fixed-die regime.Capo clearly demonstrates that despite a potential mismatch of objectives, improved mincut bisection can still lead to improved placement wirelength and congestion. Our experiments on recent industrial benchmarks fail to give a clear answer to the question in the title of this paper. However, they validate a series of improvements to recursive bisection and point out a need for transparent congestion management techniques that do not worsen the wirelength of already routable placements. Our experimental flow, which validates fixed-die placement results by violation-free detailed auto-routability, provides a new norm for comparison of VLSI placement implementations.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. J. Alpert , T. Chan , D. J.-H. Huang , I. Markov , K. Yan, Quadratic placement revisited, Proceedings of the 34th annual conference on Design automation, p.752-757, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266362]
	2	Charles J. Alpert , Jen-Hsin Huang , Andrew B. Kahng, Multilevel circuit partitioning, Proceedings of the 34th annual conference on Design automation, p.530-533, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266275]
	3	M.A. Breuer, "Min-Cut Placement", J. Design Autom. and Fault- Tolerant Comp. 1(4) (1977), pp. 343-362.
	4	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Design and implementation of move-based heuristics for VLSI hypergraph partitioning, Journal of Experimental Algorithmics (JEA), 5, p.5-es, 2000 [doi>10.1145/351827.384247]
	5	A. E. Caldwell , A. B. Kahng , I. L. Markov, Optimal partitioners and end-case placers for standard-cell layout, Proceedings of the 1999 international symposium on Physical design, p.90-96, April 12-14, 1999, Monterey, California, United States [doi>10.1145/299996.300032]
	6	A. E. Caldwell, A. B. Kahng and I. L. Markov, "VLSI CAD bookshelf", 1999, http ://vlsicad. cs. ucla. edu/GSRC/bookshelf/
	7	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Improved algorithms for hypergraph bipartitioning, Proceedings of the 2000 conference on Asia South Pacific design automation, p.661-666, January 2000, Yokohama, Japan [doi>10.1145/368434.368864]
	8	A. E. Caldwell, A. B. Kahng and I. L. Markov, "Iterative Partitioning With Varying Node Weights", to appear in VLSI Design, 2000.
	9	A. E. Caldwell and I. L. Markov, "Hierarchical Whitespace Allocation", Technical Report TR-200002, UCLA Computer Science Dept., 2000.
	10	C. K. Cheng and E. S. Kuh. "Module Placement Based on Resistive Network Optimization", IEEE Trans. on Computer Aided Design 3 (1984), pp. 218-225.
	11	Chih-Liang Eric Cheng, RISA: accurate and efficient placement routability modeling, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.690-695, November 06-10, 1994, San Jose, California, United States
	12	K. Doll, F. M. Johannes, K. J. Antreich, "Iterative Placement Improvement by Network Flow Methods", IEEE Transactions on Computer-Aided Design 13(10) (1994), pp. 1189-1200.
	13	A. E. Dunlop and B. W. Kernighan, "A Procedure for Placement of Standard Cell VLSI Circuits", IEEE Transactions on Computer- Aided Design 4(1) (1985), pp. 92-98.
	14	Shantanu Dutt , Halim Theny, Partitioning around roadblocks: tackling constraints with intermediate relaxations, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.350-355, November 09-13, 1997, San Jose, California, United States
	15	Hans Eisenmann , Frank M. Johannes, Generic global placement and floorplanning, Proceedings of the 35th annual conference on Design automation, p.269-274, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277119]
	16	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	17	Dennis J.-H. Huang , Andrew B. Kahng, Partitioning-based standard-cell global placement with an exact objective, Proceedings of the 1997 international symposium on Physical design, p.18-25, April 14-16, 1997, Napa Valley, California, United States [doi>10.1145/267665.267674]
	18	Sung-Woo Hur , John Lillis, Relaxation and clustering in a local search framework: application to linear placement, Proceedings of the 36th ACM/IEEE conference on Design automation, p.360-366, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309958]
	19	George Karypis , Rajat Aggarwal , Vipin Kumar , Shashi Shekhar, Multilevel hypergraph partitioning: application in VLSI domain, Proceedings of the 34th annual conference on Design automation, p.526-529, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266273]
	20	George Karypis , Vipin Kumar, Multilevel k-way hypergraph partitioning, Proceedings of the 36th ACM/IEEE conference on Design automation, p.343-348, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309954]
	21	J. Kleinhans, G. Sigl, F. Johannes and K. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization", IEEE Transactions on Computer-Aided Design 10(3) (1991), pp. 356-365.
	22	Tetsushi Koide , Mitsuhiro Ono , Shin'ichi Wakabayashi , Yutaka Nishimaru, A new performance driven placement method with the Elmore delay model for row based VLSIs, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.64-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan [doi>10.1145/224818.224932]
	23	Krzysztof Koźmiński, Benchmarks for layout synthesis—evolution and current status, Proceedings of the 28th conference on ACM/IEEE design automation, p.265-270, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127678]
	24	Phiroze N. Parakh , Richard B. Brown , Karem A. Sakallah, Congestion driven quadratic placement, Proceedings of the 35th annual conference on Design automation, p.275-278, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277121]
	25	Georg Sigl , Konrad Doll , Frank M. Johannes, Analytical placement: A linear or a quadratic objective function?, Proceedings of the 28th conference on ACM/IEEE design automation, p.427-432, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127707]
	26	A. Srinivasan, K. Chaudhary and E. S. Kuh, "RITUAL: A Performance Driven Placement for Small-Cell ICs", ICCAD '91, pp. 48-51.
	27	E R. Suaris and G. Kedem, "Quadrisection: A New Approach to Standard Cell Layout", ICCAD '87, pp. 474-477.
	28	Wern-Jieh Sun , Carl Sechen, Efficient and effective placement for very large circuits, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.170-177, November 07-11, 1993, Santa Clara, California, United States
	29	William Swartz , Carl Sechen, Timing driven placement for large standard cell circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.211-215, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217531]
	30	K. Takahashi, K. Nakajima, M. Terai and K. Sato, "Min-Cut Placement With Global Objective Functions for Large Scale Seaof-Gates Arrays", IEEE Transactions on Computer-Aided Design 14(4) (1995), pp. 434-446.
	31	Ren-Song Tsay , Ernest S. Kuh , Chi-Ping Hsu, PROUD: A Sea-Of-Gates Placement Algorithm, IEEE Design & Test, v.5 n.6, p.44-56, November 1988 [doi>10.1109/54.9271]
	32	E Villarrubia, G. Nusbaum, R. Masleid and ET. Patel, "IBM RISC Chip Design Methodology", ICCD '89, pp. 143-147.
	33	E Villarrubia, personal communication, 2000.
	34	Jens Vygen, Algorithms for large-scale flat placement, Proceedings of the 34th annual conference on Design automation, p.746-751, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266360]
	35	Maogang Wang , Majid Sarrafzadeh, On the behavior of congestion minimization during placement, Proceedings of the 1999 international symposium on Physical design, p.145-150, April 12-14, 1999, Monterey, California, United States [doi>10.1145/299996.300044]
	36	Maogang Wang , Sung Lim , Jason Cong , Majid Sarrafzadeh, Multi-way partitioning using bi-partition heuristics, Proceedings of the 2000 conference on Asia South Pacific design automation, p.667, January 2000, Yokohama, Japan [doi>10.1145/368434.368865]
	37	G. J. Wipfler , M. Wiesel , D. A. Mlynski, A combined force and cut algorithm for hierarchical VLSI layout, Proceedings of the 19th conference on Design automation, p.671-677, January 1982

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	P. Verplaetse , J. Dambre , D. Stroobandt , J. Van Campenhout, On partitioning vs. placement rent properties, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.33-40, March 31-April 01, 2001, Sonoma, California, United States
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	X. Yang , M. Wang , R. Kastner , S. Ghiasi , M. Sarrafzadeh, Congestion reduction during placement with provably good approximation bound, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.3, p.316-333, July 2003
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	Vishal Khandelwal , Ankur Srivastava, A quadratic modeling-based framework for accurate statistical timing analysis considering correlations, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.2, p.206-215, February 2007
	Devang Jariwala , John Lillis, Trunk decomposition based global routing optimization, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Min Pan , Chris Chu, FastRoute: a step to integrate global routing into placement, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Sarvesh H Kulkarni , Dennis Sylvester , David Blaauw, A statistical framework for post-silicon tuning through body bias clustering, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	V. Khandelwal , A. Srivastava, Leakage control through fine-grained placement and sizing of sleep transistors, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.533-536, November 07-11, 2004
	S. Chatterjee , R. Brayton, A new incremental placement algorithm and its application to congestion-aware divisor extraction, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.541-548, November 07-11, 2004
	S. N. Adya , S. Chaturvedi , J. A. Roy , D. A. Papa , I. L. Markov, Unification of partitioning, placement and floorplanning, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.550-557, November 07-11, 2004
	Bo Hu , M. Marek-Sadowska, Multilevel expansion-based VLSI placement with blockages, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.558-564, November 07-11, 2004
	A. B. Kahng , Q. Wang, An analytic placer for mixed-size placement and timing-driven placement, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.565-572, November 07-11, 2004
	K. Vorwerk , A. Kennings , A. Vannelli, Engineering details of a stable force-directed placer, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.573-580, November 07-11, 2004
	A. P. Hurst , P. Chong , A. Kuehlmann, Physical placement driven by sequential timing analysis, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.379-386, November 07-11, 2004
	Chen Li , Min Xie , Cheng-Kok Koh , J. Cong , P. H. Madden, Routability-driven placement and white space allocation, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.394-401, November 07-11, 2004
	Haoxing Ren , D. Z. Pan , P. G. Villarubia, True crosstalk aware incremental placement with noise map, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.402-409, November 07-11, 2004
	A. B. Kahng , S. Reda , Qinke Wang, Architecture and details of a high quality, large-scale analytical placer, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.891-898, November 06-10, 2005, San Jose, CA
	Haifeng Qian , S. S. Sapatnekar, A hybrid linear equation solver and its application in quadratic placement, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.905-909, November 06-10, 2005, San Jose, CA
	Y. Ran , M. Marek-Sadowska, Via-configurable routing architectures and fast design mappability estimation for regular fabrics, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.25-32, November 06-10, 2005, San Jose, CA
	Min Pan , N. Viswanathan , C. Chu, An efficient and effective detailed placement algorithm, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.48-55, November 06-10, 2005, San Jose, CA
	Kai-hui Chang , I. L. Markov , V. Bertacco, Post-placement rewiring and rebuffering by exhaustive search for functional symmetries, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.56-63, November 06-10, 2005, San Jose, CA
	J. Cong , M. Romesis , J. R. Shinnerl, Robust mixed-size placement under tight white-space constraints, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.165-172, November 06-10, 2005, San Jose, CA
	A. B. Kahng , S. Reda, Intrinsic shortest path length: a new, accurate a priori wirelength estimator, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.173-180, November 06-10, 2005, San Jose, CA
	Mehmet Can Yildiz , Patrick H. Madden, Improved cut sequences for partitioning based placement, Proceedings of the 38th conference on Design automation, p.776-779, June 2001, Las Vegas, Nevada, United States
	Andrew B. Kahng , Ion Mandoiu , Sherief Reda , Xu Xu , Alex Z. Zelikovsky, Evaluation of Placement Techniques for DNA Probe Array Layout, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.262, November 09-13, 2003
	Tony F. Chan , Jason Cong , Tim Kong , Joseph R. Shinnerl , Kenton Sze, An Enhanced Multilevel Algorithm for Circuit Placement, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.299, November 09-13, 2003
	Ameya Agnihotri , Mehmet Can YILDIZ , Ateen Khatkhate , Ajita Mathur , Satoshi Ono , Patrick H. Madden, Fractional Cut: Improved Recursive Bisection Placement, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.307, November 09-13, 2003
	Saurabh N. Adya , Igor L. Markov , Paul G. Villarrubia, On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.311, November 09-13, 2003
	Cristinel Ababei , Kia Bazargan, Placement Method Targeting Predictability Robustness and Performance, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.81, November 09-13, 2003
	Jason Cong , Tim Kong , Joseph R. Shinnerl , Min Xie , Xin Yuan, Large-Scale Circuit Placement: Gap and Promise, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.883, November 09-13, 2003
	Maogang Wang , Abhishek Ranjan , Salil Raje, Multi-Million Gate FPGA Physical Design Challenges, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.891, November 09-13, 2003
	Huaiyu Xu , Maogang Wang , Bo-Kyung Choi , Majid Sarrafzadeh, A Trade-off Oriented Placement Tool, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.467, November 09-13, 2003
	Andrew B. Kahng , Igor L. Markov , Sherief Reda, Boosting: Min-Cut Placement with Improved Signal Delay, Proceedings of the conference on Design, automation and test in Europe, p.21098, February 16-20, 2004
	Kristofer Vorwerk , Andrew Kennings, An Improved Multi-Level Framework for Force-Directed Placement, Proceedings of the conference on Design, Automation and Test in Europe, p.902-907, March 07-11, 2005
	Charles J. Alpert , Chris Chu , Paul G. Villarrubia, The coming of age of physical synthesis, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Stephen M. Plaza , Igor L. Markov , Valeria Bertacco, Optimizing non-monotonic interconnect using functional simulation and logic restructuring, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Natarajan Viswanathan , Gi-Joon Nam , Charles J. Alpert , Paul Villarrubia , Haoxing Ren , Chris Chu, RQL: global placement via relaxed quadratic spreading and linearization, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Kai-hui Chang , Igor L. Markov , Valeria Bertacco, Automating post-silicon debugging and repair, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Tao Luo , David Z. Pan, DPlace2.0: a stable and efficient analytical placement based on diffusion, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Amith Singhee , Sonia Singhal , Rob A. Rutenbar, Exploiting correlation kernels for efficient handling of intra-die spatial correlation, with application to statistical timing, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Smita Krishnaswamy , Igor L. Markov , John P. Hayes, On the role of timing masking in reliable logic circuit design, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Kai-hui Chang , Igor L. Markov , Valeria Bertacco, SafeResynth: A new technique for physical synthesis, Integration, the VLSI Journal, v.41 n.4, p.544-556, July, 2008
	Jarrod A. Roy , Aaron N. Ng , Rajat Aggarwal , Venky Ramachandran , Igor L. Markov, Solving modern mixed-size placement instances, Integration, the VLSI Journal, v.42 n.2, p.262-275, February, 2009
	Amith Singhee , Sonia Singhal , Rob A. Rutenbar, Practical, fast Monte Carlo statistical static timing analysis: why and how, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Chiu-Wing Sham , Evangeline F. Y. Young , Jingwei Lu, Congestion prediction in early stages of physical design, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.14 n.1, p.1-18, January 2009
	Liangpeng Guo , Yici Cai , Qiang Zhou , Xianlong Hong, Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.8, p.2084-2090, August 2008
	Bahareh Fathi , Laleh Behjat , Logan M. Rakai, A pre-placement net length estimation technique for mixed-size circuits, Proceedings of the 11th international workshop on System level interconnect prediction, July 26-27, 2009, San Francisco, CA, USA