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B*-Trees: a new representation for non-slicing floorplans
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents
Los Angeles, California, United States
Pages: 458 - 463  
Year of Publication: 2000
ISBN:1-58113-187-9
Authors
Yun-Chih Chang  Department of Computer and Information Science, National Chiao Tung University, Hsinchu 300, Taiwan
Yao-Wen Chang
Guang-Ming Wu  Department of Computer and Information Science, National Chiao Tung University, Hsinchu 300, Taiwan
Shu-Wei Wu
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 18,   Downloads (12 Months): 86,   Citation Count: 76
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ABSTRACT

We present in this paper an efficient, flexible, and effective data structure, B*-trees for non-slicing floorplans. B*-trees are based on ordered binary trees and the admissible placement presented in [1]. Inheriting from the nice properties of ordered binary trees, B*-trees are very easy for implementation and can perform the respective primitive tree, operations search, insertion, and deletion in only O(1), O(1), and O(n) times while existing representations for non-slicing floorplans need at least O(n) time for each of these operations, where n is the number of modules. The correspondence between an admissible placement and its induced B*-tree is 1-to-1 (i.e., no redundancy); further, the transformation between them takes only linear time. Unlike other representations for non-slicing floorplans that need to construct constraint graphs for cost evaluation, in particular, the evaluation can be performed on B*-trees and their corresponding placements directly and incrementally. We further show the flexibility of B*-trees by exploring how to handle rotated, pre-placed, soft, and rectilinear modules. Experimental results on MCNC benchmarks show that the B*-tree representation runs about 4.5 times faster, consumes about 60% less memory, and results in smaller silicon area than the O-tree one [1]. We also develop a B*-tree based simulated annealing scheme for floorplan design; the scheme achieves near optimum area utilization even for rectilinear modules.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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M. Kang and W. Dai., "General Floorplanning with L-shaped, T-shaped and Soft Blocks Based on Bounded Slicing Grid Structure," Proc. ASP-DAC, 1997.
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S. Kirkpatrick, C. D. Gelatt, and M. R Vecchi, "Optimization by Simulated Annealing," Science, vol. 220, no. 4598, May 13, 1983, pp.671-680.
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S. Nakatake, M. Furuya, and Y. Kajitani, "Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules," P1vc. ASP-DAC, pp. 571-576, 1998.
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CITED BY  76

Collaborative Colleagues:
Yun-Chih Chang: colleagues
Yao-Wen Chang: colleagues
Guang-Ming Wu: colleagues
Shu-Wei Wu: colleagues